# parsing at semantic level due to ambiguities

I have a VHDL elaboration engine/simulator. As I understand it, the language syntax allows for ambiguities at syntax level. That is, an assignment

pin_value <= bus(5)


can be interpreted as picking a child of the bus by index. Here the bus is a signal (an object). However, it can also be that paranthis are applied to a type

int_signal <= integer(1.1)


which should be interpreted as type conversion.

I wonder. The elaborator should take the parse tree, instantiate objects and tie them together resolving the names. However, the parser has no idea if the prefix at the parensis is a type or array. So, it treats all parensis as indexed objects.

simple_assignment ::= target <= value_expression { , value_expression }
value_expression ::= name | literal | function_call | type_conversion
name ::= simple_name | indexed_name
indexed_name ::= prefix ( expression { , expression } ) // example: REG_ARRAY(5)
type_conversion ::= type_mark ( expression )


I do not see how can I distinguish between value_expression and type_conversion at syntactic level. My parser parses both as indexed_name and name resolution, when fails to find array object, falls back into type conversion. I am asking if such case analysis it the only way to handle the problem or more strighnforward approach exists that I am missing?

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The ANTLR parser generator was originally designed to deal specifically with such semantic ambiguities. I'm sure that would solve all of your problems. – Dave Clarke Apr 22 '14 at 21:06
Are prefix and type_mark tokens returned by the lexer? I think the answer to your question is going to be something to the effect that you have to keep a symbol table around while doing lexing. When you read in the next token you look it up in the symbol table, which tells you whether it is a prefix, a type_mark or something else. – Wandering Logic Apr 22 '14 at 21:08