Questions about the organization and design of computer hardware.

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How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
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1answer
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Why is the processor's pipeline delay calculated as N*max(Delay) ? why not N*(D1 + D2 + D3 … )?

Consider a four stage pipeline, and each stage has delays D1, D2, D3 and D4, so the total delay because of the various stages should be N * (D1 + D2 + D3 + D4) ...
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what is computer architecture [duplicate]

I am a student learning about computer hardware, CPUs and microprocessors. I have some questions regarding computer architecture. 1) What is the term "computer architecture" mean? When someone ...
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1answer
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Question on SR latch functionality

Below is the diagram of SR latch The following is the functional table as per my scrutiny . Sl.no S | R Q(t) | Q'(t) Q(t+1) | Q'(t+1) Q(t+2) | Q'(t+2) Q(t+3) | Q'(t+3) Remark ...
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1answer
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Are interrupts needed for a computer system to work?

Are interrupts needed for a computer system to work? Could you have a computer system (hardware and software, including the OS) that worked without an interrupt mechanism?
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MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
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2answers
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How does a computer play a video while doing something else?

How is video playback done on a computer? It's obviously not relying purely on the CPU, since video playback continues when a user performs another activity, such as typing into a YouTube comment ...
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1answer
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Why use SIMD if we have GPGPU?

I thought this question is better served in the CS part of Stack Exchange. Now that we have GPGPUs with languages like CUDA and OpenCL, do the multimedia SIMD extensions (SSE/AVX/NEON) still serve a ...
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Implementation of caches on CPUs with pipelines

I've read that some current CPUs (e.g. Intel i7 and ARM A9) have (L1) cache latencies of multiple clock cycles while also being pipelined. Some devote multiple pipeline stages to instruction fetching. ...
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What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
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What is difference between architecture and microarchitecture?

I am studying computer architecture. I would like to know the difference between the terms "computer architecture" and "microarchitecture".
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Do computers actually use carry-lookahead adders?

There are plenty of details about carry lookahead adders such as Kogge-Stone, Lander-Fischer, etc. in college CS courses. They are described as "common in the industry". However, I can't find any ...
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Rotate left operation in IA 32 ISA [migrated]

How can a rotate left operation, R1 ← R2 rotate left by 7 bits, can be implemented using the IA-32 instruction set. The contents of R2 should move into R1 after being rotated by 7 bits without R2 ...
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2answers
34 views

Calculating speedup for a two-way superscalar cpu

I've been coming across a problem in one of my assignments requiring the calculation of the speedup of a two-way superscalar cpu. The problem is as follows: There is a two-way superscalar CPU with 2 ...
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1answer
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Why using Hyper-threading can lead to performance degradation

I have read it at various places like this, that Hyper-threading leads to performance degradation. I am unable to get why or how hyper-threading leads to degradation. Why it is so that even when ...
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3answers
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How does the processor find kernel code after an interrupt?

When an interrupt occurs, the processor preempts the current process and calls kernel code to handle the interrupt. How does the processor know where to enter the kernel? I understand that there are ...
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1answer
47 views

Can/Do multiple processes run simultaneously on a multi-core system?

I understand context switches and threading on a single core system, but I'm trying to understand what happens in a multi-core system. I know multiple threads from the same process can run ...
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Newly built computer refuses to show anything on the monitor [migrated]

First off, sorry if I'm posting in the wrong area, first time user of this site. Mother Board:Maximus VII Hero RAM: Trident 8GB(2x) GPU: ASUS DirectCU II CPU: Intel i7 4990k Power Supply: EVGA ...
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1answer
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K-map with don't care: increasing the number of groups instead of simplifying

AB 00 01 11 10 00 | x | 1 | 0 | 1 | CD 01 | 0 | 1 | x | 0 | 11 | 1 | x | x | 0 | 10 | x | 0 | 0 | x | The answer to the ...
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2answers
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Does the BIOS run on the CPU? [closed]

I was just thinking about this: Does the BIOS execute on the CPU? If so, how does it handle multiple CPU architectures/instruction sets? If not, what does it execute on?
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2answers
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How is data written to RAM

From my understanding(correct me if I am wrong) when I read data from RAM memory it is copied into processor cache and than it is copied into register to be used by the processor. When I create data ...
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1answer
41 views

How, in hardware, MIPS can access a word in the middle of an address

This is am example of a RAM address in the MIPS architecture (32 bits) I can imagine the RAM as having 32 pins just to inform the RAM address I want to access, so I can access each of these words ...
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How exactly the “load word” instruction loads from RAM?

PS: MIPS architecture This is a model of a memory RAM of 4GB: it has 4,294,967,295 addresses, and each address has 32 bits. Can somebody tell me why the load word instruction needs an offset to the ...
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5answers
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What are the minimum memory requirments a microprocessors must have to perform any calculation?

Please excuse my ignorance in low level things. A lot of the written below might be very wrong. As far as I understand (and I might be very wrong), there are two types of memory locations a ...
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1answer
50 views

What is the signal going from the computer to the screen? [closed]

Im sorry if it is a weird question, but I cant seem to find an answer for this. What does the signal going to the screen look like in more abstract sense? Does it code the values of each pixel in a ...
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Explanation of Tag, Index, and Offset in Direct Mapping Cache

I'm going through an exercise trying to store address references into a direct mapped cache with 128 blocks and a block size of 32 bytes. The address are 20000, 20004, 20008, and 20016 in base 10. ...
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55 views

Why aren't there computers with a base different than 2? [duplicate]

Wouldn't non-digital computers, those that use a base higher than 2, be faster and more efficient? Especially with Moore's law reaching its limit, wouldn't circuits that have three, four or five ...
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1answer
75 views

Advantages and disadvantages of microcoded vs hardcoded architectures [closed]

Preamble I can't understand what are the advantages and disadvantages of microcoded processor architecture and hardcoded one. Basically what I understood is that a microcode architecture divides an ...
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1answer
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Is running AES NI in parallel possible (one encryption per core/thread)?

AES NI seems to perform AES operations much faster than doing in software. However, if I have a machine with a large number of cores (say 32 cores), can I perform 32 AES encryptions using AES NI ...
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2answers
101 views

Why are computers so complicated? [closed]

I'm not sure this is on-topic or even the right website, please point me in the right direction if not. I was wondering why computers are so incredibly complex. This question is as naive as it ...
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1answer
108 views

Calculating miss rates of word-addressable and direct-mapped cache

This a problem in a computer architecture course that's giving me some trouble: You have an application whose memory access pattern is a stream and its entire data set is 128kB. The data cache in ...
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3answers
89 views

Additional clarification about Simultaneous Multithreading

I was looking for comments about SMT and got several responses. The last one looks strange: Simultaneous multithreading, which can only be implemented on a multicore system, executes the ...
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1answer
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Superscalar processors and complex instructions

I read that a supercalar processor has redundant functional units. One can read this e.g. on Wikipedia. How do such redundant units work? Is a complex instruction (for accelerating heavy process, ...
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2answers
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Why did MIPS include shamt and distinguish funct/opcode?

I'm confused as to why the MIPS designers would include 5 bits dedicated to shifting and have separate opcode and function bits. Because MIPS is so RISC I assume that only shifting would be done in ...
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2answers
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What is a good design for expanding opcodes?

Are there any tutorials on YouTube or good text tutorials on designing expanding opcodes? I always make mistakes on switching from one line to another and "counting" in binary. I pretty much know how ...
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3answers
528 views

Moore's law and Clock Speed

This figure says according to moore's law number of transistors doubles about two years. but clock speed, power flattening after given stage. can anyone describe the reasons this flattening in ...
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3answers
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Is a supercomputer more powerful than the total of all the world's computers in 2004?

The supercomputer I am researching has 2.2 petaflops and boasts total memory of 1000 terabytes and disk space of 23.5 petabytes. Is this more computing power than the total of the entire worlds ...
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2answers
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Why do Computers use Hex Number System at assembly language?

Why do computer use Hex Number System at assembly language? Why don't they use any other number system like binary, octal, decimal? What thing forced computer designer to use hex system at assembly? ...
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5answers
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Why Do Computers Use the Binary Number System (0,1)?

Why Do Computers Use the Binary Number System (0,1)? Why don't they use Ternary Number System (0,1,2) or any other number system instead?
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What are current cache algorithms and cache strategies?

Which cache strategies/algorithms (especially for L2 Cache) are used in practice and don't exist solely in research/theory? There is a list on Wikipedia which does not state which algorithms are ...
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Counting the number of instructions in an instruction set

An imaginary processor has the following hardware specification: 8bit data bus 12bit address bus 32 × 8bit general purpose registers e.g. S0 – ...
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Need help with a set-associative cache memory problem

I'm studying for my Computer Architecture exam next week, and I'm having problems understanding how a set associative cache works and how to solve related problems like this one : "A set-associative ...
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1answer
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Are cache contents specific to a process?

Suppose the L1 cache is filled up with data from some process. Now CPU loads another process. Does the new process share cache contents? Or the cache has to be invalidated completely in each context ...
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Can the end-to-end principle be formalized?

In the late 1990s, when I was in graduate school, the paper JH Saltzer; DP Reed; DD Clark: End-to-end arguments in system design. ACM Trans. Comput. Syst. 2(4):277-288, 1984. ...
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3answers
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Is it possible to accurately determine the number of instructions required to multiply or add two integers in a modern processor?

I'm not nearly at the experience level in computer science to be able to properly determine the number of instructions involved in basic ALU calculations, and I'm interested in a certain software ...
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What are the treatises on how to build mechanical computers?

I've just watched this replica of the Antikythera mechanism. I've heard also about Babagge's analytical machine and the Curta calculator. I got curious: What did they use to build computers made of ...
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3answers
73 views

Which architecture do modern computers use?

Is it one of: Harvard Modified Harvard von Neumann Or are they antiquated models that modern computers are only loosely based on? If you asked Intel or AMD what would they say?
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Why do servers use ECC memory? [closed]

I understand that ECC checks for errors and corrects them automatically without the knowledge of the operating system or user. I don't understand however why servers often use ECC memory?
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Simultaneous execution on a Von Neuman architecture

I have a CS course at Uni. Had an exam about two last week with a question I did not get, but still, am not totally comfortable with the expected answer. Basically, we were asked Many processes ...
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1answer
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Computer Architecture - Von Neumann

With regards to introductory (beginner) Von Neumann computer architecture, how does a program change the order in which instructions are executed? I know the control unit is responsible for ...