Questions about the organization and design of computer hardware.

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what is the software commonly used by cognitive computing engineers [on hold]

There are plenty of hardware design software such as altium designer and orcad, though these software are not designed for engineering in the cognitive computing field. ...
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1answer
23 views

How is a 2-bit predictor better than a 1-bit predictor at determining loop iterations

I have read various explanations why a 1-bit branch predictor is wrong twice per loop, once at the beginning when it wrongly predicts against entering the loop and once at the end when it wrongly ...
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1answer
18 views

Flags register in an out-of-order processor

LW R2, 0(R1) CMP R3, R2 CMP R7, R5 the LW instruction stalls the first CMP so the second one will execute first. Wouldn't this cause the flags register to contain ...
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1answer
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What's the difference between a reorder buffer and an instruction window?

In an out-of-order processor, what is the difference between a reorder buffer and an instruction window? Wikipedia says: "In particular, in a conventional design, the instruction window consists of ...
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1answer
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1answer
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What is happening in this part of the LC3? [on hold]

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...
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3answers
160 views

How was the ALU implemented in the first computer (i.e., Babbage's analytical engine)?

I've seen circuit level implementations of ALU's before, but how are NOT/AND/ADD performed mechanically?
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Which of the following instructions can reference a memory location that is #1000 locations from the instruction?

I am working on a question from a practice computer organization exam. The answer key to one of the questions says that both LD and ...
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2answers
41 views

Memory access on byte/word addressable memory

I'm doing a question on architecture and I've come across this question which I do not understand how to answer the question. Q. How many bits are required to address 4G x 32-bit main memory if a) ...
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1answer
42 views

What is this trapezoid-shaped logic component?

This is from http://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/Ch05.pdf , slide 9. From this diagram, I recognize 0001 as the opcode, which corresponds to the ADD instruction. I recognize 011, ...
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what exactly is present in CMOS when system is turned on for first time? [migrated]

also how does cmos gets all the hardware information, parameters and stores them? Does Bios writes them into CMOS or some other hardware? Bios has facility to do POST. Is this POST anyhow related to ...
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1answer
26 views

How does cpu fetch active program data (using virtual address) from storage when there is a page fault?

I read that cpu generates virtual address and using the same mmu translates to physical address and then fetches the data from RAM. But when there is a page fault, the data is fetched from the HDD(or ...
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Future register file in computer architecture

Results from the execution units are written into the future file when they complete (may be out-of-order). Upon operand fetching, you fetch from the future file and not the architectural register ...
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1answer
38 views

Can I overcome cache coherence in coding? [closed]

I know that cache coherence is the consistency of shared resource data that ends up stored in multiple local caches. Can any programming languages handle this problem? If so, how?
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Calculating Effective CPI when using write-through/write-back architecture

So I'm trying to understand a homework problem given by an instructor and I'm honestly lost - I understand the concept of write-through/write-back but, I can't figure out the actual calculations ...
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0answers
10 views

Cache Addressing

My professor has given us the following problem to solve: Consider a small computer with 16-bit registers. The memory is word addressed. There is a direct-mapped cache with 1K cache frames. ...
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1answer
36 views

Calculating the Transfer Time for a Hard Disk

I know that transfer rate is data size over transfer speed - but according to the information given, I don't know what the data size is to calculate the transfer rate. Am I missing something or was I ...
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0answers
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Cache Direct-Mapped Index&Tag

I have a question about Direct-Mapped Cache's index and tags. Below is a list of 32-bit memory address references, given as word addresses. 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61 ...
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1answer
34 views

About Control Unit in CPU and Clock Cycle

I've been studying about CPU and I am trying to implement a small CPU, like MU0. Control unit gets instruction and generates and gives several control signals to other parts of CPU, such as ALU, PC, ...
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1answer
27 views

Can each VLIW sub-instruction execute any instruction?

say that you have a 128 bit (32*4) VLIW word. Can each 32 bit sub-word contain any operation (ADD,CALL,BRANCH,...) if there are no hazards or can each sub-word only specify one functional unit (so if ...
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1answer
36 views

In which pipeline stage are exceptions detected?

Do you immediatly handle an exception when it occurs (for example an overflow exception in the EX stage) or do you wait until the final pipeline stage and then check whether any interrupts had ...
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2answers
75 views

average time to access a word in memory

Here is the question: Consider a computer system that has cache memory, main memory (RAM) and disk, and the operating system uses virtual memory. It takes 2 nsec to access a word from the cache, ...
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1answer
33 views

New Assembler in compiler [closed]

I'm currently developing my degree thesis, and the lab's idea is to design a new micro architecture, and then, be able to compile stuff for this architecture. So the question is, how do you instruct a ...
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0answers
21 views

Cache block offset

When you load data from a cache, you have to specifiy a block offset to select the byte you want. But what do you do if you don't want a single byte but a full 4 byte word?
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1answer
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Discrepancy between process execution time and CPU speed (lost cycles)

I'm not sure if this is on topic, but I've seen some hardware related questions here so I'll post it here anyway. If it's off topic I'll take it off. Compile this C code: ...
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1answer
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What data size is sent to and read from physical RAM?

When you have a cache mis, you need to fetch a block from RAM. If said block is 64 bytes big, do you need to have buses that are 512 bits (= 64 bytes) wide to transfer data from the RAM to the cache? ...
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1answer
52 views

Amdahl's law or gustafson's law

I am a little confused which of the two laws above i should use: Suppose I have a computer program that can be parallelized by 70%. 30% cannot be parallelized. Every single data (100% of data) will ...
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2answers
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Can a Von Neumann CPU be pipelined?

Can you pipeline a pure Von Neumann architecture based CPU or do you need seperate data and instruction caches for this? If you include seperate instruction and data caches (then it isn't a von ...
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How to come up with an architectural diagram for a device?

This is the question I have. You are provided with a toy military-vehicle. It can move forward, move backward, turn left, turn right, rotate clockwise, rotate anti clockwise, and fire. Each ...
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1answer
125 views

Why are comparisons so expensive on a GPU?

While trying to improve the performance of my collision detection class, I found that ~80% of the time spent at the gpu, it spent on if/else conditions just trying to figure out the bounds for the ...
18
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1answer
2k views

Is a stack overflow detected by hardware or software?

Is it the task of the software (operating system) to detect stack overflows or is a stack overflow detected in hardware, causing an exception in the CPU?
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1answer
34 views

Branch predictor question

If the branch predictor is placed in the fetch stage then how does it know that the current instruction is actually a branch before trying to predict its outcome? Is some (very little) decoding ...
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6answers
3k views

How can I academically say that 'one computer is slower than the other'?

I'm writing a research paper and I have to basically say that one microcontroller is slower than an other microprocessor. However, I'm worried that simply saying that it's 'slower' wouldn't be ...
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2answers
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How many combination of “n” bits are there in terms of n?

How many combination of "n" bits are there in terms of n? And if this is derived, Given 4 bits for representing negative and positive numbers, what is the largest positive number that can be ...
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2answers
35 views

Stack memory questions

Are data and return addresses both pushed on the same stack space? If yes, couldn't this piece of code cause problems: ...
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1answer
62 views

What counts as a pipeline?

From Tanenbaum's Structured Computer Organization: Figure 2-4(a) illustrates a pipeline with five units, also called stages. If one pipeline is good, then surely two pipelines are better. ...
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3answers
62 views

What do CPUs do when a program aborts with an error?

If a very severe interrupt occurs, say a divide by zero, this will quit the program. How is this done, is there a special instruction in the processor or is it a software routine? And after quitting ...
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5answers
114 views

How can a CPU access more memory locations than 2^wordsize?

I noticed that CPU's like the 8086 and especially the 8080 have the ability to access more memory than what one would normally assume. The 8080, for example, has an 8-bit word size but can use a ...
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1answer
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What happens when there is a branch mispredict and an interrupt occurs?

There is a branch mispredict and while executing the false code, an interrupt occurs (for example a keyboard interrupt). The EPC (register that holds the return address) now holds the wrong return ...
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5answers
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Why are reversible gates not used?

I was reading the book "The singularity is near" written by Kurzweil and he mentioned the reversible gates like for example the Fredkin gate. The advantage using such gates is that we could get rid of ...
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1answer
44 views

CPU time and execution time

Why should computer designers trade off clock rate against cycle count? Can somebody explain this sentence for me? Shouldn't it be that when the clock rate increases the cycle count decreases? I ...
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1answer
62 views

Binary digit problem?

Question: If a system has $32k$ bytes and each such byte has unique address(so $32k$ addresses), what is the smallest possible bits that can be use by every byte for the address ? All the bytes ...
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1answer
37 views

Where does the interrupt handler return to?

Say the CPU is currently handling an interrupt. Another interrupt arrives but it's lower priority than the current one so it gets put in the 'pending interrupt register'. My current interrupt is done ...
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1answer
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Direct Cache Mapping - Addressing

I've looked through all the other similar questions, but I don't feel like I understood exactly what I'm supposed to do with my case, so I'm hoping I'm not the only one. In an exercise I'm doing, I'm ...
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1answer
76 views

How do I build a read/write 4-nibble RAM memory system using flip flops?

Currently, I'm learning about flip flops and how it is used in RAM to store memory so I'm trying to recreate the circuitry in Logisim. I know the components I need which are address register, 4-bit ...
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1answer
52 views

Understanding the definition of SPMD

From Wikipedia SPMD (single program, multiple data) is a technique employed to achieve parallelism; it is a subcategory of MIMD. Tasks are split up and run simultaneously on multiple processors ...
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1answer
60 views

Why is a superscalar processor SIMD?

From http://en.wikipedia.org/wiki/Superscalar In Flynn's taxonomy, a single-core superscalar processor is classified as an SIMD processor (Single Instructions, Multiple Data), Flynn's ...
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2answers
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How do I calculate response time of a multiple core cpu when given certain information?

On my homework the question asks: A program executes serially in 200 seconds. If it is parallelized, 7 seconds of overhead are required for synchronization, locking, and communication. Compute ...
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0answers
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hybrid or “mixed” networks

I am a mathematician, and I am completely lay in the technical aspects of computer networks and computer architecture. I would like to know if there is any computer network or architecture, protocol, ...
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2answers
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Understanding Multilevel Caches

I'm reading multi-level cache and came across a question through which i got confused. I've read that Between processor and Cache Word/ Byte is transfered Between Cache and Main memory ...