Questions about the organization and design of computer hardware.

learn more… | top users | synonyms

-2
votes
0answers
37 views

direct map cache

Let's say, I have a direct mapped cache with: 1- size of 2048 KB 2- with cache line of 64 bytes 3- with 48-bit address space of the processor what is minimum number of bits that needed to store the ...
5
votes
1answer
62 views

Why are comparisons so expensive on a GPU?

While trying to improve the performance of my collision detection class, I found that ~80% of the time spent at the gpu, it spent on if/else conditions just trying to figure out the bounds for the ...
-2
votes
0answers
14 views

Mux and Decoder Examples Challenges [on hold]

i get confusing on Digital Design Course. I read on my books as an example that (1) is different from (2) to (4). anyone could describe it for me?
-3
votes
0answers
10 views

MTTF of 10,000 computers [duplicate]

If a company has 10,000 computers, each with a MTTF of 35 days, and it experiences catastrophic failure only if 1/3 of the computers fail, what is the MTTF for the system? I understand how to ...
18
votes
1answer
2k views

Is a stack overflow detected by hardware or software?

Is it the task of the software (operating system) to detect stack overflows or is a stack overflow detected in hardware, causing an exception in the CPU?
0
votes
0answers
22 views

Resolution & Pixels [closed]

Do individual pixels reduce/increase there size in respone to a change in resoulution. For example: My monitor features 1080p resolution, (1920 x 1080) If I watch a video on youtube full screen @ 720p ...
1
vote
1answer
22 views

Branch predictor question

If the branch predictor is placed in the fetch stage then how does it know that the current instruction is actually a branch before trying to predict its outcome? Is some (very little) decoding ...
11
votes
6answers
2k views

How can I academically say that 'one computer is slower than the other'?

I'm writing a research paper and I have to basically say that one microcontroller is slower than an other microprocessor. However, I'm worried that simply saying that it's 'slower' wouldn't be ...
-2
votes
0answers
43 views

how to read/write data from/to disk memory using CPU instructions? [duplicate]

Is the disk mapped to some specific RAM address, or are there instructions to read/write from/to the disk? For writing 512 bytes to disk, would you have to setup a begin address from where it will ...
0
votes
2answers
43 views

How many combination of “n” bits are there in terms of n?

How many combination of "n" bits are there in terms of n? And if this is derived, Given 4 bits for representing negative and positive numbers, what is the largest positive number that can be ...
2
votes
2answers
27 views

Stack memory questions

Are data and return addresses both pushed on the same stack space? If yes, couldn't this piece of code cause problems: ...
2
votes
1answer
44 views

What counts as a pipeline?

From Tanenbaum's Structured Computer Organization: Figure 2-4(a) illustrates a pipeline with five units, also called stages. If one pipeline is good, then surely two pipelines are better. ...
1
vote
3answers
56 views

What do CPUs do when a program aborts with an error?

If a very severe interrupt occurs, say a divide by zero, this will quit the program. How is this done, is there a special instruction in the processor or is it a software routine? And after quitting ...
1
vote
4answers
65 views

How can a CPU access more memory locations than 2^wordsize?

I noticed that CPU's like the 8086 and especially the 8080 have the ability to access more memory than what one would normally assume. The 8080, for example, has an 8-bit word size but can use a ...
3
votes
1answer
30 views

What happens when there is a branch mispredict and an interrupt occurs?

There is a branch mispredict and while executing the false code, an interrupt occurs (for example a keyboard interrupt). The EPC (register that holds the return address) now holds the wrong return ...
12
votes
5answers
2k views

Why are reversible gates not used?

I was reading the book "The singularity is near" written by Kurzweil and he mentioned the reversible gates like for example the Fredkin gate. The advantage using such gates is that we could get rid of ...
0
votes
1answer
33 views

CPU time and execution time

Why should computer designers trade off clock rate against cycle count? Can somebody explain this sentence for me? Shouldn't it be that when the clock rate increases the cycle count decreases? I ...
0
votes
1answer
35 views

Binary digit problem?

Question: If a system has $32k$ bytes and each such byte has unique address(so $32k$ addresses), what is the smallest possible bits that can be use by every byte for the address ? All the bytes ...
1
vote
1answer
26 views

Where does the interrupt handler return to?

Say the CPU is currently handling an interrupt. Another interrupt arrives but it's lower priority than the current one so it gets put in the 'pending interrupt register'. My current interrupt is done ...
0
votes
1answer
14 views

Direct Cache Mapping - Addressing

I've looked through all the other similar questions, but I don't feel like I understood exactly what I'm supposed to do with my case, so I'm hoping I'm not the only one. In an exercise I'm doing, I'm ...
0
votes
1answer
55 views

How do I build a read/write 4-nibble RAM memory system using flip flops?

Currently, I'm learning about flip flops and how it is used in RAM to store memory so I'm trying to recreate the circuitry in Logisim. I know the components I need which are address register, 4-bit ...
0
votes
1answer
25 views

Understanding the definition of SPMD

From Wikipedia SPMD (single program, multiple data) is a technique employed to achieve parallelism; it is a subcategory of MIMD. Tasks are split up and run simultaneously on multiple processors ...
2
votes
1answer
39 views

Why is a superscalar processor SIMD?

From http://en.wikipedia.org/wiki/Superscalar In Flynn's taxonomy, a single-core superscalar processor is classified as an SIMD processor (Single Instructions, Multiple Data), Flynn's ...
1
vote
2answers
49 views

How do I calculate response time of a multiple core cpu when given certain information?

On my homework the question asks: A program executes serially in 200 seconds. If it is parallelized, 7 seconds of overhead are required for synchronization, locking, and communication. Compute ...
0
votes
0answers
17 views

hybrid or “mixed” networks

I am a mathematician, and I am completely lay in the technical aspects of computer networks and computer architecture. I would like to know if there is any computer network or architecture, protocol, ...
0
votes
2answers
48 views

Understanding Multilevel Caches

I'm reading multi-level cache and came across a question through which i got confused. I've read that Between processor and Cache Word/ Byte is transfered Between Cache and Main memory ...
2
votes
0answers
25 views

What happens when many interrupt requests happen at the same time?

My initial guess is that you would have to queue the lower priority one, but what happens when for example 5 or many more requests happen at the same time? Are all these requests put in a queue or are ...
1
vote
1answer
45 views

how 16 bits address lines address 64KB?

" The 8080 was an 8-bit CPU, meaning it processed 8 bits of information at a time. However, it had 16 address lines coming out of it. The ‘‘bitness’’ of a CPU—how many bits wide its general-purpose ...
1
vote
0answers
17 views

Having a problem understanding the execution of I/O in Von Neumann model

I might have gone too deep in my search after the answer which might be much easier than what I figured. Essentially I wanted to figure out how I/O are executed in a Von Neumann machine, but more I ...
-1
votes
1answer
225 views

MTTF (mean time to failure) of 10,000 computers

Here is a question in my textbook I am having trouble with. This is actually not homework --- I just don't understand how to get the solution for this one: If a company has 10,000 computers, each ...
2
votes
2answers
86 views

Why is Computer Architecture in $2^n$ bits?

I have always wondered why is computer architecture in $2^n$ bits. We have 8 / 16 / 32 / 64-bit microprocessors or for that matter other parts of computer are also in power of 2 bits. The only logic ...
0
votes
1answer
24 views

How to compute max jump distance

I have a BNE-instruction (32 bits), which contains 16 bits for the jump field: Opcode A[31:26] RS A[25:21] RT A[20:16] Immed A[15:0] Assuming the BNE-instruction will now be written in 64 bits ...
-1
votes
1answer
42 views

calculate the effective (average) access time (E AT) of this system

A computer with a single cache (access time 40ns) and main memory (access time 200ns) also uses the hard disk (average access time 0.02 ms) for virtual memory pages. If it is found that the cache hit ...
0
votes
1answer
20 views

How to count bits in cache (direct & 4-way)

Let's say, I have a cache with: 2^32 bytes of memory 2048 blocks (of 16 bytes each) Now I'm trying to figure out how much bits each field will contain. Direct mapped: One block is 16 bytes (16 ...
1
vote
1answer
19 views

Identical register input operands in assembly

The question is not specific to any processor. Can I have an assembly instruction, like: ADD R1 R0 R0 R1 is the destination. ...
-1
votes
1answer
18 views

computer organization : finding control word length

A microprogram control unit is required to generate a total of 35 control signals. Assume that during any microinstruction, at most 2 control signals are active. The minimum number of bits required in ...
0
votes
1answer
45 views

What is the theoretical speedup with pipeline system over a nonpipelined system?

What is the theoretical speedup that could be achieved with the pipeline system over a nonpipelined system? The equation I use for speedup is $$ S = \frac{nT}{(k+n-1)t}\,$$ where: $n$ is the ...
1
vote
0answers
25 views

Reverse Polish to infix

I have to convert "A = B C + D E + ×" from reverse polish to infix notation. I'm a bit confused because of the equals sign. Is that an operator too? This is my answer: A = (B+C) x (D+E) Is this ...
1
vote
1answer
53 views

Why do some architectures use a CMP instruction before branching while others just branch?

My initial guess is that you will have more instruction space for the immediate in your branch instruction when you first use a CMP instruction. However, you have to use 2 instructions each time you ...
0
votes
1answer
25 views

Do I require loading in this example of load store architecture?

I'm currently revising for my Concurrent Programming exam and I'm going through the past papers and one question poses the following process: ...
-1
votes
2answers
69 views

What are the disadvantages of having many registers?

IA-64 is an architecture that has 128 general purpose registers, are there any disadvantages (beside being more expensive and larger instruction size) to having many registers?
-1
votes
1answer
31 views

2's complement addition with ZF/Carry/Overflow

Consider addition of two numbers when CPU uses $2's$ complement form: $$ 1\ 1\ 0\ 0\ 0\ 0\ 1\ 1\\0\ 1\ 0\ 0\ 1\ 1\ 0\ 0\\-------\\0\ 0\ 0\ 0\ 1\ 1\ 1\ 1\\------- $$ $$Carry\ = 1,\ Overflow = ...
7
votes
3answers
140 views

Why is the CPU Involved During Keyboard Echo?

I'm currently studying for a computer science exam, and I've come across a concept that has me somewhat stumped. When one types a key on the keyboard, an ASCII character is transmitted to the CPU. ...
4
votes
3answers
780 views

Is order of bits in byte really not of concern?

What I can't wrap my head around is sentence repeated everywhere I look, that order of bits in byte is not important(not of my, as a programmer, concern). My question then is if there is possibility ...
0
votes
2answers
67 views

Understanding Instruction Cycle?

A basic instruction cycle consists of these 5 stages. Instruction Cycle IF - Instruction Fetch RD - Instruction Decode and Register Read EX - Execute MA - Memory Access WB - Write ...
-1
votes
1answer
36 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
0
votes
1answer
35 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
0
votes
0answers
28 views

How to load the program counter and make it an input?

I have been assigned to create a basic Y86 processor for a project. I have most of it done, all I'm missing is a couple of instructions. The pcmmovl and mpcmovl instructions are where I'm stuck at. ...
2
votes
1answer
75 views

How does the Program Counter work?

I think it stores the address of the current instruction. And if this instruction is completed the program counter is incremented by 1, to get the next instruction. But now my question is, how do you ...
0
votes
0answers
46 views

Tag, index and offset of associative cache

My main issue of a homework problem is trying to figure out the different parts of the chart. I have a 3 way set associative cache with 2 word blocks, total size of 24 words. I am given 3, 180, 43, 2, ...