Questions about the organization and design of computer hardware.

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1answer
15 views

Can i install Firefox OS apps in android? [on hold]

I saw some cool apps in the firefox webstore & i want them in my android.please can anyone help me with this.
1
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2answers
38 views

How do I calculate response time of a multiple core cpu when given certain information?

On my homework the question asks: A program executes serially in 200 seconds. If it is parallelized, 7 seconds of overhead are required for synchronization, locking, and communication. Compute ...
0
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0answers
16 views

hybrid or “mixed” networks

I am a mathematician, and I am completely lay in the technical aspects of computer networks and computer architecture. I would like to know if there is any computer network or architecture, protocol, ...
0
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2answers
35 views

Understanding Multilevel Caches

I'm reading multi-level cache and came across a question through which i got confused. I've read that Between processor and Cache Word/ Byte is transfered Between Cache and Main memory ...
2
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0answers
23 views

What happens when many interrupt requests happen at the same time?

My initial guess is that you would have to queue the lower priority one, but what happens when for example 5 or many more requests happen at the same time? Are all these requests put in a queue or are ...
-1
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0answers
13 views

Understanding Register Opeation [on hold]

Can we store address in MBR which can only store data $$MBR \leftarrow PC$$ $$MAR \leftarrow X$$ $$PC \leftarrow Y$$ $$Memory \leftarrow MBR$$ I've read that PC(Program Counter) holds the ...
1
vote
1answer
25 views

how 16 bits address lines address 64KB?

" The 8080 was an 8-bit CPU, meaning it processed 8 bits of information at a time. However, it had 16 address lines coming out of it. The ‘‘bitness’’ of a CPU—how many bits wide its general-purpose ...
1
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0answers
12 views

Having a problem understanding the execution of I/O in Von Neumann model

I might have gone too deep in my search after the answer which might be much easier than what I figured. Essentially I wanted to figure out how I/O are executed in a Von Neumann machine, but more I ...
0
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0answers
47 views

MTTF (mean time to failure) of 10,000 computers

Here is a question in my textbook I am having trouble with. This is actually not homework --- I just don't understand how to get the solution for this one: If a company has 10,000 computers, each ...
-2
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0answers
19 views

effective access time with right through policy

effective access time = cache_access_time+ miss probability*time to transfer a line between cache and main memory+ fraction _of_right_references(memory_access_time - cache_access_time) using ...
2
votes
2answers
69 views

Why is Computer Architecture in $2^n$ bits?

I have always wondered why is computer architecture in $2^n$ bits. We have 8 / 16 / 32 / 64-bit microprocessors or for that matter other parts of computer are also in power of 2 bits. The only logic ...
1
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0answers
13 views

Register Adressing vs. PC-relative adressing

Could somebody explain me the difference between Register Addressing and PC-relative addressing? Like how the PC-value increases with an instruction? Thanks in advance!
0
votes
1answer
20 views

How to compute max jump distance

I have a BNE-instruction (32 bits), which contains 16 bits for the jump field: Opcode A[31:26] RS A[25:21] RT A[20:16] Immed A[15:0] Assuming the BNE-instruction will now be written in 64 bits ...
-1
votes
1answer
22 views

calculate the effective (average) access time (E AT) of this system

A computer with a single cache (access time 40ns) and main memory (access time 200ns) also uses the hard disk (average access time 0.02 ms) for virtual memory pages. If it is found that the cache hit ...
0
votes
1answer
18 views

How to count bits in cache (direct & 4-way)

Let's say, I have a cache with: 2^32 bytes of memory 2048 blocks (of 16 bytes each) Now I'm trying to figure out how much bits each field will contain. Direct mapped: One block is 16 bytes (16 ...
1
vote
1answer
18 views

Identical register input operands in assembly

The question is not specific to any processor. Can I have an assembly instruction, like: ADD R1 R0 R0 R1 is the destination. ...
-1
votes
1answer
14 views

computer organization : finding control word length

A microprogram control unit is required to generate a total of 35 control signals. Assume that during any microinstruction, at most 2 control signals are active. The minimum number of bits required in ...
0
votes
1answer
42 views

What is the theoretical speedup with pipeline system over a nonpipelined system?

What is the theoretical speedup that could be achieved with the pipeline system over a nonpipelined system? The equation I use for speedup is $$ S = \frac{nT}{(k+n-1)t}\,$$ where: $n$ is the ...
1
vote
0answers
22 views

Reverse Polish to infix

I have to convert "A = B C + D E + ×" from reverse polish to infix notation. I'm a bit confused because of the equals sign. Is that an operator too? This is my answer: A = (B+C) x (D+E) Is this ...
0
votes
1answer
29 views

Why do some architectures use a CMP instruction before branching while others just branch?

My initial guess is that you will have more instruction space for the immediate in your branch instruction when you first use a CMP instruction. However, you have to use 2 instructions each time you ...
0
votes
1answer
19 views

Do I require loading in this example of load store architecture?

I'm currently revising for my Concurrent Programming exam and I'm going through the past papers and one question poses the following process: ...
-1
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2answers
45 views

What are the disadvantages of having many registers?

IA-64 is an architecture that has 128 general purpose registers, are there any disadvantages (beside being more expensive and larger instruction size) to having many registers?
0
votes
1answer
18 views

2's complement addition with ZF/Carry/Overflow

Consider addition of two numbers when CPU uses $2's$ complement form: $$ 1\ 1\ 0\ 0\ 0\ 0\ 1\ 1\\0\ 1\ 0\ 0\ 1\ 1\ 0\ 0\\-------\\0\ 0\ 0\ 0\ 1\ 1\ 1\ 1\\------- $$ $$Carry\ = 1,\ Overflow = ...
6
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3answers
116 views

Why is the CPU Involved During Keyboard Echo?

I'm currently studying for a computer science exam, and I've come across a concept that has me somewhat stumped. When one types a key on the keyboard, an ASCII character is transmitted to the CPU. ...
4
votes
3answers
763 views

Is order of bits in byte really not of concern?

What I can't wrap my head around is sentence repeated everywhere I look, that order of bits in byte is not important(not of my, as a programmer, concern). My question then is if there is possibility ...
0
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2answers
60 views

Understanding Instruction Cycle?

A basic instruction cycle consists of these 5 stages. Instruction Cycle IF - Instruction Fetch RD - Instruction Decode and Register Read EX - Execute MA - Memory Access WB - Write ...
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1answer
24 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
0
votes
1answer
26 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
0
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0answers
21 views

How to load the program counter and make it an input?

I have been assigned to create a basic Y86 processor for a project. I have most of it done, all I'm missing is a couple of instructions. The pcmmovl and mpcmovl instructions are where I'm stuck at. ...
2
votes
1answer
46 views

How does the Program Counter work?

I think it stores the address of the current instruction. And if this instruction is completed the program counter is incremented by 1, to get the next instruction. But now my question is, how do you ...
0
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0answers
39 views

Tag, index and offset of associative cache

My main issue of a homework problem is trying to figure out the different parts of the chart. I have a 3 way set associative cache with 2 word blocks, total size of 24 words. I am given 3, 180, 43, 2, ...
1
vote
1answer
179 views

Cache Direct Map (Index, tag, hit/miss)

Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which ...
0
votes
1answer
29 views

MIPS with one read port in the register file?

I'm studying the MIPS multi-cycle datapath, and I'm wondering what would happen if there was only one read port in the register file for certain instructions. First, for R-type instructions, I know ...
2
votes
1answer
43 views

What is oblivious RAM and how does it work?

Could anybody explain me what exactly oblivious RAM is? I found the following explanation which makes it kind of clear to me, but I would like to get a sense of the technical aspects: Encryption ...
0
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0answers
33 views

SCAN and CSCAN algorithms of disk scheduling

I am having hard time understanding the working of SCAN and CSCAN algorithm of disk scheduling.I understood FCFS,Closest Cylinder Next but heard that SCAN resembles elevator mechanism and got ...
0
votes
1answer
44 views

Conversion from Decimal form to BCD

I have seen a way how to convert a decimal number to BCD (packed & unpacked) using 8,4,2,1 weighing forms but how to do it using 4,2,2,1 and 7,4,2,1 ? Any method please.Suggestions
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1answer
27 views

How was counted one second in computers

I would like to know how was counted 1 second in computers. I mean how machine can understand period of 1 second. Who and when resolved this problem, and more important how ?
0
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1answer
96 views

Why are computers so reliable?

In any complicated system, there is always some scope for error. When I program on my computer, the system computes perfectly each time. 1+1 always turns out to be 2. We take reliability of the ...
0
votes
1answer
64 views

How to calculate the miss ratio of a cache

I know how to calculate the CPI or cycles per instruction from the hit and miss ratios, but I do not know exactly how to calculate the ...
0
votes
2answers
72 views

Examples of an I/O interface

In computer architecture class, my lecturer was explaining about I/O interfaces and modules, but somehow neither me nor my classmates understood almost a word he said.. We still don't get which parts ...
1
vote
1answer
31 views

Origin of tFAW (Four Activation Window) in DRAM timing constraint

In DRAM timing constraints, tFAW means length of a rolling window that allows up to four row activations in same Rank. This constraint is mainly due to power budget of each rank. However, I am ...
0
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0answers
91 views

Booth's Algorithm Multiplication

When multiplying signed integers by Booth's algorithm, does the multiplicand always have to be negative? What happens if multiplier and multiplicand are both negative? Does the algorithm still work? ...
1
vote
1answer
37 views

Isn't software needed from programs to run? [closed]

I am a student who has entered a game programming competition called FBLA at school, and I sent them an email because I had a few questions about how the competition is ran. The main question I had, ...
7
votes
2answers
112 views

why do CPU architectures use a flags register (advantages?)

Some CPUs have a flags register (ARM,x86,...), others don't (MIPS,...). What's the advantage of having a CMP instruction to update the flags register followed by a branch instruction instead of using ...
0
votes
1answer
48 views

Interpret bits as a signed integer in 2s complement

Imagine you load this data as a 4-byte word into a register R. What is the value in R on a big endian machine and what is it ...
0
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0answers
42 views

How would the MIPS instruction set change if there were only eight registers?

For MIPS, what if there were only 8 registers instead of the 32 that there are, and the immediate constants were 12 bits instead of 16? I know that the size of an instruction changes depending on ...
0
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1answer
43 views

Is the “data path cycle” the same thing of the “fetch-decode-execute cycle”?

I am reading the book Structured Computer Organization (5th edition) by Tanenbaum and at a certain point, in the second chapter, he talks about ...
0
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0answers
28 views

Relationship between #of cores and Dynamic Power

The book I'm currently reading specifies that Dynamic Power = (1/2) * Capacitive Load * (V^2) * frequency However, that is assuming it's a single-core system. I ...
2
votes
1answer
75 views

Does register renaming remove all kinds of WAR hazard?

For the following two instruction [Note: MOV Destination, Source ] i1 : MOV R1, R2 i2 : ADD R2, R3 Since i1 is reading from R2 and i2 is writing to R2 there is ...
0
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1answer
68 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...