Questions about the organization and design of computer hardware.

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1answer
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Can each VLIW sub-instruction execute any instruction?

say that you have a 128 bit (32*4) VLIW word. Can each 32 bit sub-word contain any operation (ADD,CALL,BRANCH,...) if there are no hazards or can each sub-word only specify one functional unit (so if ...
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0answers
19 views

Placing data on the bus for a synchronous read operation

This question is taken from Computer Organization and architecture, William Stalling: For a synchronous read operation (Figure 3.18), the memory module must place the data on the bus sufficiently ...
2
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1answer
28 views

In which pipeline stage are exceptions detected?

Do you immediatly handle an exception when it occurs (for example an overflow exception in the EX stage) or do you wait until the final pipeline stage and then check whether any interrupts had ...
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1answer
51 views

Computer making company? [closed]

I am 15 and I want to make a company. I have wanted to for years. I found some friends with this interest too. We have 3 CEOs. 2 to make decisions and a 3rd for a tiebreaker. We have established we ...
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2answers
47 views

average time to access a word in memory

Here is the question: Consider a computer system that has cache memory, main memory (RAM) and disk, and the operating system uses virtual memory. It takes 2 nsec to access a word from the cache, ...
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1answer
32 views

New Assembler in compiler [closed]

I'm currently developing my degree thesis, and the lab's idea is to design a new micro architecture, and then, be able to compile stuff for this architecture. So the question is, how do you instruct a ...
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0answers
17 views

Cache block offset

When you load data from a cache, you have to specifiy a block offset to select the byte you want. But what do you do if you don't want a single byte but a full 4 byte word?
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1answer
23 views

Discrepancy between process execution time and CPU speed (lost cycles)

I'm not sure if this is on topic, but I've seen some hardware related questions here so I'll post it here anyway. If it's off topic I'll take it off. Compile this C code: ...
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1answer
30 views

What data size is sent to and read from physical RAM?

When you have a cache mis, you need to fetch a block from RAM. If said block is 64 bytes big, do you need to have buses that are 512 bits (= 64 bytes) wide to transfer data from the RAM to the cache? ...
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1answer
44 views

Amdahl's law or gustafson's law

I am a little confused which of the two laws above i should use: Suppose I have a computer program that can be parallelized by 70%. 30% cannot be parallelized. Every single data (100% of data) will ...
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2answers
61 views

Can a Von Neumann CPU be pipelined?

Can you pipeline a pure Von Neumann architecture based CPU or do you need seperate data and instruction caches for this? If you include seperate instruction and data caches (then it isn't a von ...
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0answers
25 views

How to come up with an architectural diagram for a device?

This is the question I have. You are provided with a toy military-vehicle. It can move forward, move backward, turn left, turn right, rotate clockwise, rotate anti clockwise, and fire. Each ...
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0answers
47 views

direct map cache

Let's say, I have a direct mapped cache with: 1- size of 2048 KB 2- with cache line of 64 bytes 3- with 48-bit address space of the processor what is minimum number of bits that needed to store the ...
7
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1answer
116 views

Why are comparisons so expensive on a GPU?

While trying to improve the performance of my collision detection class, I found that ~80% of the time spent at the gpu, it spent on if/else conditions just trying to figure out the bounds for the ...
18
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1answer
2k views

Is a stack overflow detected by hardware or software?

Is it the task of the software (operating system) to detect stack overflows or is a stack overflow detected in hardware, causing an exception in the CPU?
1
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1answer
31 views

Branch predictor question

If the branch predictor is placed in the fetch stage then how does it know that the current instruction is actually a branch before trying to predict its outcome? Is some (very little) decoding ...
11
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6answers
3k views

How can I academically say that 'one computer is slower than the other'?

I'm writing a research paper and I have to basically say that one microcontroller is slower than an other microprocessor. However, I'm worried that simply saying that it's 'slower' wouldn't be ...
0
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2answers
53 views

How many combination of “n” bits are there in terms of n?

How many combination of "n" bits are there in terms of n? And if this is derived, Given 4 bits for representing negative and positive numbers, what is the largest positive number that can be ...
2
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2answers
29 views

Stack memory questions

Are data and return addresses both pushed on the same stack space? If yes, couldn't this piece of code cause problems: ...
2
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1answer
50 views

What counts as a pipeline?

From Tanenbaum's Structured Computer Organization: Figure 2-4(a) illustrates a pipeline with five units, also called stages. If one pipeline is good, then surely two pipelines are better. ...
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3answers
58 views

What do CPUs do when a program aborts with an error?

If a very severe interrupt occurs, say a divide by zero, this will quit the program. How is this done, is there a special instruction in the processor or is it a software routine? And after quitting ...
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4answers
81 views

How can a CPU access more memory locations than 2^wordsize?

I noticed that CPU's like the 8086 and especially the 8080 have the ability to access more memory than what one would normally assume. The 8080, for example, has an 8-bit word size but can use a ...
3
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1answer
34 views

What happens when there is a branch mispredict and an interrupt occurs?

There is a branch mispredict and while executing the false code, an interrupt occurs (for example a keyboard interrupt). The EPC (register that holds the return address) now holds the wrong return ...
12
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5answers
2k views

Why are reversible gates not used?

I was reading the book "The singularity is near" written by Kurzweil and he mentioned the reversible gates like for example the Fredkin gate. The advantage using such gates is that we could get rid of ...
0
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1answer
40 views

CPU time and execution time

Why should computer designers trade off clock rate against cycle count? Can somebody explain this sentence for me? Shouldn't it be that when the clock rate increases the cycle count decreases? I ...
0
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1answer
47 views

Binary digit problem?

Question: If a system has $32k$ bytes and each such byte has unique address(so $32k$ addresses), what is the smallest possible bits that can be use by every byte for the address ? All the bytes ...
1
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1answer
29 views

Where does the interrupt handler return to?

Say the CPU is currently handling an interrupt. Another interrupt arrives but it's lower priority than the current one so it gets put in the 'pending interrupt register'. My current interrupt is done ...
0
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1answer
20 views

Direct Cache Mapping - Addressing

I've looked through all the other similar questions, but I don't feel like I understood exactly what I'm supposed to do with my case, so I'm hoping I'm not the only one. In an exercise I'm doing, I'm ...
0
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1answer
64 views

How do I build a read/write 4-nibble RAM memory system using flip flops?

Currently, I'm learning about flip flops and how it is used in RAM to store memory so I'm trying to recreate the circuitry in Logisim. I know the components I need which are address register, 4-bit ...
0
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1answer
35 views

Understanding the definition of SPMD

From Wikipedia SPMD (single program, multiple data) is a technique employed to achieve parallelism; it is a subcategory of MIMD. Tasks are split up and run simultaneously on multiple processors ...
2
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1answer
48 views

Why is a superscalar processor SIMD?

From http://en.wikipedia.org/wiki/Superscalar In Flynn's taxonomy, a single-core superscalar processor is classified as an SIMD processor (Single Instructions, Multiple Data), Flynn's ...
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2answers
55 views

How do I calculate response time of a multiple core cpu when given certain information?

On my homework the question asks: A program executes serially in 200 seconds. If it is parallelized, 7 seconds of overhead are required for synchronization, locking, and communication. Compute ...
0
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0answers
17 views

hybrid or “mixed” networks

I am a mathematician, and I am completely lay in the technical aspects of computer networks and computer architecture. I would like to know if there is any computer network or architecture, protocol, ...
0
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2answers
53 views

Understanding Multilevel Caches

I'm reading multi-level cache and came across a question through which i got confused. I've read that Between processor and Cache Word/ Byte is transfered Between Cache and Main memory ...
2
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0answers
25 views

What happens when many interrupt requests happen at the same time?

My initial guess is that you would have to queue the lower priority one, but what happens when for example 5 or many more requests happen at the same time? Are all these requests put in a queue or are ...
1
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1answer
77 views

how 16 bits address lines address 64KB?

" The 8080 was an 8-bit CPU, meaning it processed 8 bits of information at a time. However, it had 16 address lines coming out of it. The ‘‘bitness’’ of a CPU—how many bits wide its general-purpose ...
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0answers
20 views

Having a problem understanding the execution of I/O in Von Neumann model

I might have gone too deep in my search after the answer which might be much easier than what I figured. Essentially I wanted to figure out how I/O are executed in a Von Neumann machine, but more I ...
-1
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1answer
280 views

MTTF (mean time to failure) of 10,000 computers

Here is a question in my textbook I am having trouble with. This is actually not homework --- I just don't understand how to get the solution for this one: If a company has 10,000 computers, each ...
3
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2answers
108 views

Why is Computer Architecture in $2^n$ bits?

I have always wondered why is computer architecture in $2^n$ bits. We have 8 / 16 / 32 / 64-bit microprocessors or for that matter other parts of computer are also in power of 2 bits. The only logic ...
0
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1answer
28 views

How to compute max jump distance

I have a BNE-instruction (32 bits), which contains 16 bits for the jump field: Opcode A[31:26] RS A[25:21] RT A[20:16] Immed A[15:0] Assuming the BNE-instruction will now be written in 64 bits ...
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1answer
64 views

calculate the effective (average) access time (E AT) of this system

A computer with a single cache (access time 40ns) and main memory (access time 200ns) also uses the hard disk (average access time 0.02 ms) for virtual memory pages. If it is found that the cache hit ...
0
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1answer
24 views

How to count bits in cache (direct & 4-way)

Let's say, I have a cache with: 2^32 bytes of memory 2048 blocks (of 16 bytes each) Now I'm trying to figure out how much bits each field will contain. Direct mapped: One block is 16 bytes (16 ...
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1answer
22 views

Identical register input operands in assembly

The question is not specific to any processor. Can I have an assembly instruction, like: ADD R1 R0 R0 R1 is the destination. ...
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1answer
22 views

computer organization : finding control word length

A microprogram control unit is required to generate a total of 35 control signals. Assume that during any microinstruction, at most 2 control signals are active. The minimum number of bits required in ...
0
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1answer
51 views

What is the theoretical speedup with pipeline system over a nonpipelined system?

What is the theoretical speedup that could be achieved with the pipeline system over a nonpipelined system? The equation I use for speedup is $$ S = \frac{nT}{(k+n-1)t}\,$$ where: $n$ is the ...
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0answers
27 views

Reverse Polish to infix

I have to convert "A = B C + D E + ×" from reverse polish to infix notation. I'm a bit confused because of the equals sign. Is that an operator too? This is my answer: A = (B+C) x (D+E) Is this ...
1
vote
1answer
56 views

Why do some architectures use a CMP instruction before branching while others just branch?

My initial guess is that you will have more instruction space for the immediate in your branch instruction when you first use a CMP instruction. However, you have to use 2 instructions each time you ...
0
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1answer
30 views

Do I require loading in this example of load store architecture?

I'm currently revising for my Concurrent Programming exam and I'm going through the past papers and one question poses the following process: ...
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2answers
94 views

What are the disadvantages of having many registers?

IA-64 is an architecture that has 128 general purpose registers, are there any disadvantages (beside being more expensive and larger instruction size) to having many registers?
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1answer
36 views

2's complement addition with ZF/Carry/Overflow

Consider addition of two numbers when CPU uses $2's$ complement form: $$ 1\ 1\ 0\ 0\ 0\ 0\ 1\ 1\\0\ 1\ 0\ 0\ 1\ 1\ 0\ 0\\-------\\0\ 0\ 0\ 0\ 1\ 1\ 1\ 1\\------- $$ $$Carry\ = 1,\ Overflow = ...