Questions about the organization and design of computer hardware.

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difference between data rate and baud rate

what is difference between data rate and baud rate?? can anyone one explain this example also??(specifically e.g for data rate) E.g. Suppose 110 bits are transmitted per second and 11 bit frames are ...
0
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1answer
31 views

Conversion from Decimal form to BCD

I have seen a way how to convert a decimal number to BCD (packed & unpacked) using 8,4,2,1 weighing forms but how to do it using 4,2,2,1 and 7,4,2,1 ? Any method please.Suggestions
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1answer
24 views

How was counted one second in computers

I would like to know how was counted 1 second in computers. I mean how machine can understand period of 1 second. Who and when resolved this problem, and more important how ?
0
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1answer
64 views

Why are computers so reliable?

In any complicated system, there is always some scope for error. When I program on my computer, the system computes perfectly each time. 1+1 always turns out to be 2. We take reliability of the ...
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0answers
18 views

What are logical/physical records and sectors?

I try to understand the following definitions but currently I feel like a sinking ship. For example: What is a record ? What is a logical- and physical-record ? Concerning the physical-record I ...
0
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1answer
25 views

How to calculate the miss ratio of a cache

I know how to calculate the CPI or cycles per instruction from the hit and miss ratios, but I do not know exactly how to calculate the ...
0
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2answers
28 views

Examples of an I/O interface

In computer architecture class, my lecturer was explaining about I/O interfaces and modules, but somehow neither me nor my classmates understood almost a word he said.. We still don't get which parts ...
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0answers
8 views

Origin of tFAW (Four Activation Window) in DRAM timing constraint

In DRAM timing constraints, tFAW means length of a rolling window that allows up to four row activations in same Rank. This constraint is mainly due to power budget of each rank. However, I am ...
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0answers
55 views

Booth's Algorithm Multiplication

When multiplying signed integers by Booth's algorithm, does the multiplicand always have to be negative? What happens if multiplier and multiplicand are both negative? Does the algorithm still work? ...
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1answer
29 views

Isn't software needed from programs to run? [closed]

I am a student who has entered a game programming competition called FBLA at school, and I sent them an email because I had a few questions about how the competition is ran. The main question I had, ...
7
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2answers
82 views

why do CPU architectures use a flags register (advantages?)

Some CPUs have a flags register (ARM,x86,...), others don't (MIPS,...). What's the advantage of having a CMP instruction to update the flags register followed by a branch instruction instead of using ...
0
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1answer
40 views

Interpret bits as a signed integer in 2s complement

Imagine you load this data as a 4-byte word into a register R. What is the value in R on a big endian machine and what is it ...
0
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0answers
33 views

How would the MIPS instruction set change if there were only eight registers?

For MIPS, what if there were only 8 registers instead of the 32 that there are, and the immediate constants were 12 bits instead of 16? I know that the size of an instruction changes depending on ...
0
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1answer
29 views

Is the “data path cycle” the same thing of the “fetch-decode-execute cycle”?

I am reading the book Structured Computer Organization (5th edition) by Tanenbaum and at a certain point, in the second chapter, he talks about ...
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0answers
20 views

Relationship between #of cores and Dynamic Power

The book I'm currently reading specifies that Dynamic Power = (1/2) * Capacitive Load * (V^2) * frequency However, that is assuming it's a single-core system. I ...
0
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0answers
111 views

Computer Architecture: DFS and DVFS problem

The question: You have a large inventory of Intel processors that run at 3 GHz and 1 Volt, and consume 100 W (of which, 20 W is leakage) when running a given CPU-bound application. This application ...
2
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1answer
51 views

Does register renaming remove all kinds of WAR hazard?

For the following two instruction [Note: MOV Destination, Source ] i1 : MOV R1, R2 i2 : ADD R2, R3 Since i1 is reading from R2 and i2 is writing to R2 there is ...
0
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1answer
57 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
2
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1answer
70 views

Why is the processor's pipeline delay calculated as N*max(Delay) ? why not N*(D1 + D2 + D3 … )?

Consider a four stage pipeline, and each stage has delays D1, D2, D3 and D4, so the total delay because of the various stages should be N * (D1 + D2 + D3 + D4) ...
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1answer
34 views

Question on SR latch functionality

Below is the diagram of SR latch The following is the functional table as per my scrutiny . Sl.no S | R Q(t) | Q'(t) Q(t+1) | Q'(t+1) Q(t+2) | Q'(t+2) Q(t+3) | Q'(t+3) Remark ...
0
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1answer
73 views

Are interrupts needed for a computer system to work?

Are interrupts needed for a computer system to work? Could you have a computer system (hardware and software, including the OS) that worked without an interrupt mechanism?
4
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2answers
112 views

Will the future quantum computers use the binary, ternary or quaternary numeral system?

Our current computers use bits, so they use the binary numeral system. But I heard that the future quantum computers will use qubits instead of simple bits. Since in the word "qubit" there is the ...
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0answers
25 views

MIPS limited dual issue

Some of the MIPS processors like 5kc, 5kf have "limited dual issue". Searching online it seems that this means that the processor allows for a dual issue in only some selected cases, but it is not ...
4
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2answers
122 views

How does a computer play a video while doing something else?

How is video playback done on a computer? It's obviously not relying purely on the CPU, since video playback continues when a user performs another activity, such as typing into a YouTube comment ...
3
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1answer
71 views

Why use SIMD if we have GPGPU?

I thought this question is better served in the CS part of Stack Exchange. Now that we have GPGPUs with languages like CUDA and OpenCL, do the multimedia SIMD extensions (SSE/AVX/NEON) still serve a ...
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1answer
44 views

Implementation of caches on CPUs with pipelines

I've read that some current CPUs (e.g. Intel i7 and ARM A9) have (L1) cache latencies of multiple clock cycles while also being pipelined. Some devote multiple pipeline stages to instruction fetching. ...
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3answers
1k views

What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
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1answer
95 views

What is difference between architecture and microarchitecture?

I am studying computer architecture. I would like to know the difference between the terms "computer architecture" and "microarchitecture".
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1answer
140 views

Do computers actually use carry-lookahead adders?

There are plenty of details about carry lookahead adders such as Kogge-Stone, Lander-Fischer, etc. in college CS courses. They are described as "common in the industry". However, I can't find any ...
2
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1answer
27 views

How are system calls handled in a virtual machine?

Quoting wikipedia, a system call is: In computing, a system call is how a program requests a service from an operating system's kernel. This may include hardware related services (e.g. ...
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2answers
91 views

Calculating speedup for a two-way superscalar cpu

I've been coming across a problem in one of my assignments requiring the calculation of the speedup of a two-way superscalar cpu. The problem is as follows: There is a two-way superscalar CPU with 2 ...
10
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5answers
21 views

Why is the OS design able to reduce power consumption?

I have read that OSes like Android and iOS are somehow optimised to improve battery life. My understanding is that a CPU executes a certain number of operations in a certain time, so I would think ...
7
votes
1answer
20 views

Why using Hyper-threading can lead to performance degradation

I have read it at various places like this, that Hyper-threading leads to performance degradation. I am unable to get why or how hyper-threading leads to degradation. Why it is so that even when ...
9
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3answers
35 views

How does the processor find kernel code after an interrupt?

When an interrupt occurs, the processor preempts the current process and calls kernel code to handle the interrupt. How does the processor know where to enter the kernel? I understand that there are ...
0
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1answer
101 views

Can/Do multiple processes run simultaneously on a multi-core system?

I understand context switches and threading on a single core system, but I'm trying to understand what happens in a multi-core system. I know multiple threads from the same process can run ...
3
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1answer
66 views

K-map with don't care: increasing the number of groups instead of simplifying

AB 00 01 11 10 00 | x | 1 | 0 | 1 | CD 01 | 0 | 1 | x | 0 | 11 | 1 | x | x | 0 | 10 | x | 0 | 0 | x | The answer to the ...
2
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2answers
66 views

Does the BIOS run on the CPU? [closed]

I was just thinking about this: Does the BIOS execute on the CPU? If so, how does it handle multiple CPU architectures/instruction sets? If not, what does it execute on?
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2answers
78 views

How is data written to RAM

From my understanding(correct me if I am wrong) when I read data from RAM memory it is copied into processor cache and than it is copied into register to be used by the processor. When I create data ...
2
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1answer
64 views

How, in hardware, MIPS can access a word in the middle of an address

This is am example of a RAM address in the MIPS architecture (32 bits) I can imagine the RAM as having 32 pins just to inform the RAM address I want to access, so I can access each of these words ...
1
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2answers
72 views

How exactly the “load word” instruction loads from RAM?

PS: MIPS architecture This is a model of a memory RAM of 4GB: it has 4,294,967,295 addresses, and each address has 32 bits. Can somebody tell me why the load word instruction needs an offset to the ...
2
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5answers
60 views

What are the minimum memory requirments a microprocessors must have to perform any calculation?

Please excuse my ignorance in low level things. A lot of the written below might be very wrong. As far as I understand (and I might be very wrong), there are two types of memory locations a ...
4
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1answer
50 views

What is the signal going from the computer to the screen? [closed]

Im sorry if it is a weird question, but I cant seem to find an answer for this. What does the signal going to the screen look like in more abstract sense? Does it code the values of each pixel in a ...
1
vote
1answer
140 views

Explanation of Tag, Index, and Offset in Direct Mapping Cache

I'm going through an exercise trying to store address references into a direct mapped cache with 128 blocks and a block size of 32 bytes. The address are 20000, 20004, 20008, and 20016 in base 10. ...
0
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1answer
65 views

Why aren't there computers with a base different than 2? [duplicate]

Wouldn't non-digital computers, those that use a base higher than 2, be faster and more efficient? Especially with Moore's law reaching its limit, wouldn't circuits that have three, four or five ...
1
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1answer
141 views

Advantages and disadvantages of microcoded vs hardcoded architectures [closed]

Preamble I can't understand what are the advantages and disadvantages of microcoded processor architecture and hardcoded one. Basically what I understood is that a microcode architecture divides an ...
2
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1answer
43 views

Is running AES NI in parallel possible (one encryption per core/thread)?

AES NI seems to perform AES operations much faster than doing in software. However, if I have a machine with a large number of cores (say 32 cores), can I perform 32 AES encryptions using AES NI ...
0
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2answers
163 views

Why are computers so complicated? [closed]

I'm not sure this is on-topic or even the right website, please point me in the right direction if not. I was wondering why computers are so incredibly complex. This question is as naive as it ...
0
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1answer
167 views

Calculating miss rates of word-addressable and direct-mapped cache

This a problem in a computer architecture course that's giving me some trouble: You have an application whose memory access pattern is a stream and its entire data set is 128kB. The data cache in ...
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3answers
98 views

Additional clarification about Simultaneous Multithreading

I was looking for comments about SMT and got several responses. The last one looks strange: Simultaneous multithreading, which can only be implemented on a multicore system, executes the ...
2
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1answer
88 views

Superscalar processors and complex instructions

I read that a supercalar processor has redundant functional units. One can read this e.g. on Wikipedia. How do such redundant units work? Is a complex instruction (for accelerating heavy process, ...