Organization and design of computer hardware.

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Computer Architecture: control pins, CE OE [migrated]

Just understanding some syntax. On my Ram (6116) and Rom (27C64) it has a asserted low CE and OE pins. These I believe are control pins. I'm assuming to use the RAM for example, chip enable (ce) has ...
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What is the difference between Inclusive and Non-Inclusive Cache? [on hold]

Inclusive cache is one where cache at each level(L1, L2, L3 etc) contains same information at any point of time, whereas ...
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36 views

Computer Architecture - Von Neumann

With regards to introductory (beginner) Von Neumann computer architecture, how does a program change the order in which instructions are executed? I know the control unit is responsible for ...
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Is there anything lower than the bit level of 1s and 0s?

When learning about the architecture of computers and how it works, we are thought that the lowest language that we can find that the machine understands is binary as 1&0. And anything that we ...
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35 views

Which kind of interrupt has the highest priority on 8086 processors? [closed]

Which of the following interrupts has the highest priority in 8086 micro-processor: Overflow, NMI or Type 255? The book I read suggests that type 255 has highest priority. But most of the searches ...
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Basics of endianness for memory access

So I am rewriting this to make it clear so I will start with one question I have a problem that states Consider a 32-bit hexadecimal number stored in memory as follows: ...
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1answer
38 views

Is my understanding of kernels correct?

System: Application OS: Scheduler, VMM, IPC, FS Drivers, dispatchers, VFS The above would be a monolithic kernel. In a monolithic kernel all core OS functions are separate from user spaaaaaace. ...
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5 views

Branch Prediction - LOCAL BHR without tag

I have a question about the common course "Computer Architecture". How is it possible to have a LOCAL Branch Predecitor with 1024 entries, 3 bits for HISTORY but without a TAG. As I understand,in ...
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32 views

Caches: connection between a given code and a cache

I have completed a computer architecture course and the last topic i have learned was cache memories. I have peeked in random tests of course from the last few years and all of them have a given mips ...
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Memory latency, bank busy time and stride in vector architecture

The question I ask is in reference to the Appendix G of Hennessy Patterson 4th Edition computer architecture book. On page G-23, it is written that if there are 64 memory banks and the stride is 32 ...
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3answers
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Does exploiting a spatial Locality in Cache always leads to a lower miss rate?

I've read that, incorporating many words(spatial locality) per cache blocks leads to lower miss rate. Is it the case always? One possibility of such approach is to make a single cache block of size ...
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Why does x86 has explicit register definitions, and RISC's doesn't?

For example, on x86, we have a set of general registers, each named to the function it carries out. We have an Accumulator, which is a storage for a results of different fixed point operations, we ...
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Heterogenous and Asymmetric Computing's differences

The definition of the both architecture looks pretty same. They are parallel computing architecture with different type of cores. What distinguish their definition, actually?
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MIPS: sign extend in I-Type commands

My lecturer told me that when I use an arithmetic I-Type command (ADDI,SUBI etc.) , the IMM field gets sign extended, and when I use a logic I-Type command (ORI,ANDI etc.) , the IMM field is just ...
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Critical path of MIPS single cycle CPU

I'm doing the exercises from "Computer Organization and Design, Fourth Edition: The Hardware and Software Interface" by David Patterson and John Hennessy. I've come across a problem that states: ...
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Why does a processor have 32 registers?

I've always wondered why processors stopped at 32 registers. It's by far the fastest piece of the machine, why not just make bigger processors with more registers? Wouldn't that mean less going to the ...
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36 views

A question from Computer Organization on Peak Clock Frequency

Given below are 3 different pipelined processors: $P_1:\ 4\ stages\ with\ delays\ \ \ \ 0.6_{ms}\ \ 0.8_{ms}\ \ 0.6_{ms}\ \ 1.1_{ms}\\ P_2:\ 4\ stages\ with\ delays\ \ \ \ 2.0_{ms}\ \ 1.8_{ms}\ \ ...
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1answer
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Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
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3answers
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Execution time of an uneven pipeline

I was trying to solve a question dealing with n instructions in an uneven pipeline with k stages. I came across a generic formula for even pipelines i.e. (k + n - 1) * clock cycle. But I feel this ...
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1answer
49 views

What happens at the decode phase of the instruction cycle?

I am reading about the various phases of the Instruction Execution, I found out that we have three phases like below. Fectch Decode Execute Now if the part I don't understand is why do we need a ...
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1answer
43 views

branch prediction buffer - 5 stage integer MIPS [closed]

will you recommend use of branch prediction buffers for 5 stage integer MIPS pipeline. Does this increase the efficiency or not?
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MIPS Architecture : PC-relative addressing [duplicate]

In case of branch Instructions such as beq, bne, we use PC-relative addressing. But I am not clear why it is said in most of the ...
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2answers
56 views

MIPS Architecture : PC-relative addressing

In case of branch Instructions such as beq, bne, we use PC-relative addressing. But I am really not clear why it is said in ...
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Is there any defined programming model for 'Self-Learning' NPUs?

Qualcomm is creating a Neuromorphic Processing Unit or an NPU called zeroth. IBM is also working on a brain inspired chip under Synapse program. Standford's Neurogrid might be a similar example. ...
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Why do we need so many transistors in a chip, and how are they managed?

My knowledge is very vague as all we have are visual diagrams etc, but we have memory address and registers, the ALU being the heart(apparently). Single core CPUs process one instruction at a time ...
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Problem in finding the floating point representation?

So, i was trying: $(-10.75)_{10}$ and to convert it into 32 bit binary floating point representation. i did this: According to IEEE standard: $(-1)^{-s} * 1.M * 2^{E-bias} $ ...
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Query about FP Divide latency and Initiation Interval

Latency is defined as the number of intervening cycles between an instruction that produces a result and an instruction that uses the result. The initiation or repeat interval is the number of cycles ...
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How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
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2answers
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What is Simultaneous Multithreading

I come from an electronics background. I know that there are three types of implementations of multithreading (see Computer Architecture: A Quantitative Approach, 5th Edition): Fine-grain ...
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Instruction Set Architecture- Question [duplicate]

So this is a homework question but I have some solution and I am just confused, so a detailed example or help would be nice. You are designing the instruction set for a new type of computer. The ...
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161 views

Information Set Architecture Question

Yes, this is a homework question, I've tried working it out and was hoping I could get pointed in the right direction. Here's the question: You are designing the instruction set for a new type of ...
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1answer
248 views

Word- or byte-addressable? Correct terminology

Seemingly, a byte has established itself to be 8bit (is that correct?). RAM and NOR-flash can be normally accessed on a quite granular level, but it is up to the system architecture to determine if ...
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45 views

use of unconditional transfer of control instruction

I did not understand why unconditional transfer of control instruction is used in cpu.So if we already know we have to jump to an instruction and skip some instruction irrespective of any condition ...
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2answers
112 views

Difference between memory access and write-back in RISC pipeline

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline. We learned in class these following assumptions: ...
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Finding TLB hit and miss [duplicate]

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nsec and servicing a page fault takes 8 millisec. An average instruction takes 100 nsec of CPU time and two ...
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33 views

Owned state in MOESI protocol-transitions?

I understand that MESI is a subset of the MOESI cache coherency protocol. But what does the Owned state in the MOESI protocol represent? What are the differences in state transition due to the extra ...
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131 views

Size of address registers and data registers in relation with memory size

Suppose that a processor can address directly up to 4 Gigabyte main memory and can operate words with size 32 bit. Find how big should be the size of the "MAR" (memory address registers), "MDR" ...
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67 views

Is it possible to do multitasking without context switch with just one cpu?

All the article I can find seems to talk about multitasking and context switch as its a two different thing. It seems that multitasking and context switch are the same thing.
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1answer
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How does a TLB and data cache work?

I'm trying to study for an exam and I realized I'm confused about how the TLB and data cache work. I understand that the TLB is essentially a cache of most recently used physical addresses. However, ...
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What is the lower bound of the following computation

I came across this question was I was browsing online An operation OP has the following characteristics OP Latency = 7 clocks OP cycles/issue =2 Derive ...
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What is “memory coalescing”?

I came to know that the graphic processing unit have something called memory coalescing. On reading on it I was not clear on the topic. Is this any way related to Memory Level Parallelism. I have ...
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Flowcharts vs DFA resp FSM equivalency

First I apologize if I confused therms DFA and FSM, to me it seems that is the same thing. The question is simple: Are the flowcharts (sequence, branching and jumping) equivalent to DFA resp. FSM? I ...
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54 views

Subtracting binaries using two's complement

I am trying to subtract these two binary numbers: $ 1110 - 1011$ First I convert 1011 to two's complement by doing 1011 to 0100 and then adding 1 to get 0101. Then I add the first number to the ...
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Why is the Mean Time To Failure of multiple disks calculated via division and not multiplication?

I am reading about disk redudancy. I read the following: Suppose that the mean time to failure of a disk is 100,000 hours. Then the mean time to failure of some disk in an array of 100 disks ...
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What are the cache mapping algorithms used for?

Are they used for saving the information; sending the information to the processor or finding the information? (or something else) Edit: I am talking about the direct, fully assotiative and set ...
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Is there a prefered name for the “effective access time” formula?

Any CS class about caches will at some point address this classical formula (or a variant of it) Effective_access_time = hit_time + miss_penalty * miss_rate My ...
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835 views

Average Memory Access Time for Split/2-Level Cache

I am trying to calculate the average memory access time of a 2-level cache with a split L1 cache. I am given the 3 formulas below: Given Basic Formula: ...
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188 views

least significant bit,and most significant bit

if a,b are both binary bit. a=0, and b=0, what is least significant bit,and most significant bit of a+b, which means 0+0? if c is the carry bit, and c=1, what is the least significant bit,and most ...
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214 views

Confused by Floating Point Spacing

I'm currently taking a numerical analysis class in college and we're covering floating point systems. For the most part, I have a good grasp on it. However, something I can't seem to visualize, and ...
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Approximate percentage of the memory's total operating time for refreshes while refreshing DRAM

A DRAM that must be given a refresh cycle 64 times per ms.Each refresh requires 150ns,a memory cycle requires 250 ns. What is the approximate percentage of the memory's total operating time must be ...