Questions related to the design of computer hardware.
4
votes
2answers
77 views
Why do most books say that a 1 bit branch predictor mispredicts on the first loop iteration?
I am reading two books, Computer organization and design by David A Patterson, and Digital Design and Computer Architecture by Harris and Harris. These books claim that a 1 bit branch predictor ...
1
vote
0answers
28 views
The relation between privileged instructions, traps and system calls [migrated]
I am trying to understand how a virtual machine monitor (VMM) virtualizes the CPU.
My understanding right now is that the CPU issues a protection fault interrupt when a privileged instruction is ...
4
votes
1answer
64 views
Is there an affordable experiment which shows chips can't get much smaller? [closed]
If I am correct, chips cannot get much smaller because of Heisenberg's uncertainty principle. My friend and I want to perform an experiment (which is cheap, i.e. doesn't require million-dollar ...
2
votes
1answer
43 views
Realtime hardware/software versus PC software/hardware, how are these distinct and alike? [closed]
This question stems from a few answers and comments on a question I posted in signal processing found here.
I guess I am a little confused. Are there any concrete differences between realtime ...
0
votes
0answers
31 views
ripple carry full adder
A 1-bit ripple carry full adder uses 7 AND gates in parallel at the first level of inputs and use 2 OR gates at the second level.If each gate has the propagation delay = .002 micro second , then the ...
-2
votes
0answers
19 views
Why does it take more time to download a file inside a virtualized OS? [closed]
I downloaded a file in my regular OS. I needed the same file in a virtualized OS. It took way more time in the virtualized OS. I ran both in parallel and the same thing happened again.
What is the ...
1
vote
1answer
97 views
How to evaluate the clock cycle for MIPS single cycle CPU
The Situation
I'm trying to read the book 'Digital Design Computer Architecture'.
In the part of Performance Analysis(7.3.4 in the book), Author refers to clock cycle for MIPS single cycle processor. ...
0
votes
1answer
47 views
Finding cache block transfer time in a 3 level memory system
Following question was asked in one of entrance exams for a graduation programme. Please help me try to solve it :
A computer system has an L1 cache, an L2 cache, and a main memory
unity ...
3
votes
1answer
45 views
Why we need EEPROM in this micro-controller
PIC16F887 Block Diagram
According to the block diagram above, since we already have Program Memory, which may be used to store our program, why should we still need EEPROM? What is it for?
0
votes
0answers
51 views
Finding hit ratio of a cache
Consider an array A[100] & each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. Assume one block is read into ...
-2
votes
1answer
21 views
Computer Organization related to Virtual Memory [closed]
I want a formula for Effective Access Time (EAT) to access a location in main memory with following parameters:
MAT = memory access time,
TLBT = TLB access time,
PFT = page fault service time,
h = ...
3
votes
2answers
94 views
How DMA improves I/O operation efficiency?
I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. Stallings pretty well explains why Programmed I/O (CPU keeps checking the I/O module register ...
-4
votes
2answers
57 views
Binary Substraction Operation Closed Over The Set Of Natural Numbers [closed]
HISTORY AND REASONING (skip to BINARY OPERATION for actual question)
British mathematician Francis Maseres claimed that negative numbers:
"... darken the very whole doctrines of the equations and ...
1
vote
1answer
48 views
Computer Architecture-3 level RAM hierarchy
In all computer architecture books we study that Cache memory could be divided into 3 levels (L1,L2 and L3) and its very beneficial to do so. Why don't we use the same approach in case of main memory ...
4
votes
1answer
57 views
Perfect shuffle in parallel processing
How is Perfect shuffle a better interconnect scheme for parallel processing? For example if we consider a problem of sum reduction, I want to understand how this scheme is useful when implementing sum ...
-1
votes
2answers
67 views
Network modem question
How would I solve the following can anyone help me.I know MIPS is basically how many instruction the processor can do per second but what should I do?
Assume that we are receiving a message across a ...
4
votes
4answers
186 views
1
vote
1answer
286 views
Fastest mode of data transfer
Which of the following modes of data transfer is the fastest?
a. DMA
b. Interrupt-based
c. Polling
d. All are equally fast
I do not have the answer, so I cannot check, that's why I am posting ...
4
votes
2answers
74 views
Time units required for Interrupt Cycle
I am reading William Stallings Computer Organization & Architecture to understand about control unit & micro-operations.
Stallings explain that interrupt cycle requires 3 time units to ...
4
votes
3answers
71 views
CPU Cache is managed by which software component?
CPU caches are used by exploiting temporal and spatial locality. My question is who is responsible for managing these caches? Is this Operating system that identifies a particular access pattern and ...
0
votes
0answers
20 views
Mean time to failure calculation help [duplicate]
Given this formula how do you calculate the following? I don't understand, can some one explain?
...
2
votes
2answers
136 views
What is the system's mean time to failure?
I have the following homework problem:
A 10 TB disk drive has an MTTF of 6,000,000 hours. How much data can we store in a system comprised of these disks, if we want the system MTTF to be at ...
3
votes
2answers
115 views
The amount of ROM needed to implement a 4-bit multiplier?
For a 4-bit multiplier there are $2^4 \cdot 2^4 = 2^8$ combinations.
The output of 4-bit multiplication is 8 bits, so the amount of ROM needed is $2^8 \cdot 8 = 2048$ bits.
Why is that? Why does ...
-5
votes
1answer
50 views
Can anyone express the number 215 in the 32-bit floating point format IEEE-754 [closed]
i would be most grateful if you could solve this question
Thank you
1
vote
3answers
64 views
Does the write through cache copies the whole block or just the byte which is updated?
Just a basic question to ask
Does the write through cache copies the whole block or just the byte which is updated?
I went through the following question
Array A contains 256 elements of 4 bytes ...
2
votes
1answer
26 views
Where do these DRAM row/column calculations come from?
Let r be the number of rows in a DRAM array, and c be the number of columns.
Apparently, DRAM with organization 16x1 requires least pins when r = c = 4 because fewer address bits are required to ...
6
votes
1answer
141 views
Theoretical minimum number of registers for a modern computer?
I took a course on compilers in my undergraduate studies in which we wrote a compiler that compiles source programs in a toy Java-like language to a toy assembly language (for which we had an ...
1
vote
1answer
57 views
categories of registers and and storage in them
The Wikipedia article on processor registers mentions:
Address registers hold addresses and are used by instructions that indirectly access primary memory.
Which addresses does this sentence ...
14
votes
7answers
969 views
How does the computer determine whether a number is smaller or greater than another?
It might sound like a stupid question but I'm really curious to know how a computer knows that $1<2$? Also, how does a computer know that the order of integer is $1,2,3,4,5,\ldots$ and alphabet is ...
0
votes
2answers
979 views
Doubt regarding cache hit ratios and access time
Question 1: What is the average access time for a 3-level memory system with access time $T_1$, $2T_1$ and $3T_1$? (Hit ratio $h_1$ = $h_2$ = 0.9)
The solution given is: $0.9[T_1] + 0.1(0.9[2*T_1] + ...
0
votes
0answers
65 views
What is the easiest programming language to simulate a computer architecture? [closed]
What is the simplest computer language I can use to simulate a SIMD multiprocessor system if the # of processing elements, # of memory units, and an interconnection network is specified?
The ...
6
votes
2answers
184 views
Mathematical model on which current computers are built
It is said that "The Turing machine is not intended as practical computing technology, but rather as a hypothetical device representing a computing machine. Turing machines help computer scientists ...
2
votes
2answers
80 views
Commonly used Error Correcting Codes
We know error correcting codes are parameterized as (n,k,d) codes. I wanted to know the values of these parameters for some commonly used error correcting codes in computer memories or in DRAMs, etc.
...
3
votes
1answer
108 views
How do you go about designing a vector processor architecture for the sum of matrix products?
The following equation is a matrix expression where $B_i$ and $C_i^T$ are $n\times n$ matrices and k is a positive integer:
$$P = \sum_{i=1}^k B_i C_i^T $$
So $P = B_1 C_1^T + B_2 C_2^T + \cdots ...
0
votes
1answer
83 views
How to determine the Utilization and Efficiency of a file server?
I have shown my work below for the problem and would appreciate if someone can let me know if I'm on the right track or point me in the right direction if not.
An 8 processor file server handles a ...
3
votes
1answer
236 views
Using Amdahl's law how do you determine execution time after an improvement?
Speeding up a new floating-point unit by 2 slows down data cache accesses by a factor of 2/3 (or a 1.5 slowdown for data caches). If old FP unit took 20% of program's execution time and data cache ...
0
votes
1answer
142 views
How to convert process / cpu core based upon MIPS?
I want to know how can i find number of cpu cores/processor supported given i have the MIPS value?
For e.g I want to know the number of matching cores/processor to process speed of 18 triilion ...
5
votes
3answers
324 views
Why floating point representation uses a sign bit instead of 2's complement to indicate negative numbers
Consider a fixed point representation which can be regarded as a degenerate case of a floating number. It is entirely possible to use 2's complement for negative numbers. But why is a sign bit ...
4
votes
1answer
42 views
Indirection in IAS computer
From Computer Organisation and Architecture:
The IAS operates by repetitively performing an instruction cycle. Each
instruction cycle consists of two sub cycles. During a fetch cycle,
the ...
3
votes
1answer
85 views
Could I simulate the implementation of memory components
I am currently reading the IEEE paper A Memory-Efficient Parallel String Matching
Architecture for High-Speed Intrusion Detection by Kai Zheng, Bin Liu, Xin Zhang, and Yunhao Liu.
In the paper ...
1
vote
0answers
87 views
Object-based distributed Operating systems [closed]
Can any one explain how object-based technology used in distributed operating systems?
Also can any one suggest any learning resources (links, slideshows, e-books etc) to learn about Amoeba OS?
1
vote
0answers
104 views
Has Little Endian won? [closed]
When teaching recently about the Big vs. Little Endian battle, a student asked whether it had been settled, and I realized I didn't know. Looking at the Wikipedia article, it seems that the most ...
11
votes
5answers
597 views
How does a computer work?
Ok, I have been a computer nerd for many many years. I can program in quite a few languages, and I can even build them. I sat down with a buddy the other day and asked how a computer actually takes ...
5
votes
1answer
125 views
Why can L3 caches hold only shared blocks?
In a recent CACM article [1], the authors present a way to improve scalability of shared and coherent caches. The core ingredient is assuming the caches are inclusive, that is higher-level caches ...
2
votes
1answer
518 views
Theoretical speed gain of quad core vs. single core
I first asked this question at cstheory, but they suggested to ask my question here, so here it goes ...
I'm working on my masters thesis and I need to have theoretical value of the (average) speed ...
3
votes
5answers
407 views
Ternary processing instead of Binary
Most of the computers available today are designed to work with binary system. It comes from the fact that information comes in two natural form, true or false.
We humans accept another form of ...
7
votes
1answer
153 views
When do structural hazards occur in pipelined architectures?
I'm looking for some relatively simple examples of when structural hazards occur in a pipelined architecture.
The only scenario I can think of is when memory needs to be accessed during different ...
4
votes
1answer
103 views
What techniques exist for energy-efficient computing and networking?
I am currently reviewing the potentials of cloud computing regarding energy efficiency and green IT. In connection with this review I am having a look on techniques for increasing energy-efficiency in ...
9
votes
2answers
147 views
Organisation and Architecture of Quantum Computers
What are devices and their interconnections used alongwith Quantum Processors? Are they compatible with hardware devices like Cache, RAM, Disks of current computers?
4
votes
1answer
175 views
Big-Endian/Little-Endian argument - paper by Danny Cohen
Reading a book I was redirected to "On holy wars and a plea for peace" paper by Danny Cohen, which covers the "holy war" between big-endians and little-endians considering byte-order.
Reaching the ...
