Questions about the organization and design of computer hardware.

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1answer
16 views

Is the front-side bus multiplier the same as how many transfers it does per second?

What I am doing: I've been reading there about front-side busses (FSB) and their cycles per second (MHz) vs. bandwidth (Millions of Transactions per second or MT/s). What I've understood: FSB's MHz ...
0
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0answers
6 views

Changing Partition scheme [migrated]

I want to change my partition scheme from MBR to GUID. Is there a way to do this without any data loss. I have Windows 8 installed. Will my OS boot after changing the partition scheme?? Thank you..
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0answers
18 views

Computer architecture: addressing modes [on hold]

need help in this question.... Assume indirect addressing mode is used with n levels of indirection. How many memory accesses are required to obtain the target value ? A) n B) n-1 C) n+1 D) 1 E) ...
0
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1answer
8 views

Register Transfer Activity

In a simple architecture(not considering parallel architecture) how exactly this can be performed in a single clock cycle: P:R1 <- R2, R2 <-R1 where R1 and R2 are registers and P is a control ...
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0answers
17 views

how to find number of automata when states are given? [on hold]

two states q0 and q1 are given in which q0 initiates over {a,b} find. i) no of FA which accept empty string ii)possible no of DFA with states q0 and q1.
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0answers
19 views

How to solve this question?? question given in image [on hold]

This is the question given in image related to comp architecture i got no clue how to solve it. not even how to start solving it . A step by step explanation is appreciated
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0answers
12 views

How much time required to read 1024 bytes of data in programmed input mode cpu? [on hold]

can anyone sole it ? i dont get any clue how to solve it. i also posted the same question on yahoo but don't get an answer here is the link you can refer . ...
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0answers
18 views

how to solve this question ?? [on hold]

There are 64 general purpose registers in a system and instruction size is 16 bits. If there are 10 two address instructions, then how many one address instructions are possible?
0
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1answer
29 views

Why don't 2 GPUs double the graphics performance of a computer compared to a single GPU?

Obviously, if you have 2 GPUs, it is double the hardware, and thus it should be double the power of a single GPU (assuming all GPUs are the same, of course). So why is this not the case? I searched ...
0
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2answers
55 views

Where is Program Counter (PC) stored?

Where is program counter stored? CPU caches? Also how big are these counters? What happens if that memory has been filled up? I know that it's a value that stores the next instruction for the CPU ...
1
vote
1answer
85 views

What is memcomputing?

In recent article of PM the memcomputing is presented. But I did not understand how it works, according to the text. What is the general principle of work for this ...
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1answer
56 views

How is the micro code executed within a processor?

How does the microprocessor convert the machine code to micro code? What part of the processor is at play?
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0answers
22 views

What is an adaptive cache prefetching policy?

what is meant by the term "adaptive cache prefetching policy" and how is it different from regular methods of prefetching a cache? what are the advantages of adaptive cache prefetching?
0
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1answer
33 views

pipeline execution time

Lets suppose that 20 percent of the instructions in a program are branch instructions.The static prediction of the jumps supposes that the jumps don't happen. I should find the execution time in two ...
0
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1answer
27 views

Pipelining and Preemption

According to the concepts of Pipelining, In a single cycle different stages of different instructions are executed. Now I have a bit of confusion here, that if a single processing element is ...
0
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1answer
27 views

MU0 instruction set

As i know the MU0 processor instruction format is as follows: so the opcode is 4 bit, can anyone explain why it has only 8 instructions, if it could have 16 instructions, 2^4 = 16 ??
0
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1answer
36 views

RAW Data Hazard resolution

Let's consider the following MIPS (using pipelined arch.) assembly code: lw r1,0(r2) sub r4, r1, r6 and r6, r1, r7 or r8, r1, r9 the r1 value used in the second ...
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votes
1answer
29 views

How does this instruction format limit the number of memory addresses? [closed]

I have come across a question like this. And I don't have any idea how to solve this. Suppose a machine with instruction format of the form opcode A,B,R where ...
2
votes
3answers
40 views

Who converts binary/machine code to electrical signals and how?

I went through lots of blogs and posts but could not exactly figure out how the machine code is converted to electrical signals? Any software program is compiled to machine code which is nothing but ...
12
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2answers
147 views

purpose of supercomputers

Last fall I went on a tour of the Blue Waters supercomputer at the University of Illinois. I asked whether anyone ever used the entire computer. I was told that it was always working on multiple ...
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1answer
37 views

AMAT question cache here [closed]

Suppose that the processor reads cache memory in one clock cycle.In case of cache miss the processor needs 5 clock cycles to read the information in the main memory.What should be the value of Cache ...
0
votes
1answer
76 views

How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
2
votes
2answers
96 views

Is a 2 address machine more likely to follow a RISC or CISC design?

The Problem: If I have a 3 address machine, is my machine more likely to follow RISC or CISC design? 2 addresses? 1 address? 0 address. To solve this problem I first looked up the different ...
0
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0answers
31 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
0
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0answers
49 views

What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
2
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1answer
121 views

what are the key advantages of pipelining

I was trying to look my book computer architecture and design, but I can not find the answer for this question. what are-the key-advantages of pipelining?
2
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0answers
59 views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
-1
votes
1answer
25 views

the name of state when data reading from hard drive [closed]

In computer organization and architecture, what is the name of the state when data must be read from hard drive? I have tried to search it on StackOverflow and textbooks but could not find the answer. ...
5
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2answers
80 views

What happens when the words transfered on the bus are smaller than its width?

So what happens if we're transfering lots of 8 bit words in a 32 bit bus? Does each bus cycle only transfers 8 bit at the time, wasting the other 24 lines of the bus? Or does it transfer 4 words in ...
2
votes
2answers
83 views

Advantage of byte addressable memory over word addressable memory

What is the reason that almost all computers (besides some DSPs) use byte addressable memory? With byte addressable memory and a 32 bit address you can have 4GB while with word addressable memory you ...
0
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1answer
34 views

speed, cost and capacity tradoff

I'm reading William Stalling's Operating System Design and internals. Talking about memory, the following tradeoff was introduced: As might be expected, there is a tradeoff among the three key ...
1
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1answer
27 views

comparison in speed between the processor and the hard disk

I'm reading through William Stalling's operating system intrnals and design principles book. Talking about interrupts, it gives the following examples when comparing the speed of a processor and a ...
0
votes
1answer
111 views

Computer Architecture, cache hit and misses

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. One of the ...
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votes
2answers
61 views

Computer Architecture, specifically Amdahl's Law

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. The question I ...
1
vote
0answers
76 views

Loading a word from a byte addressed cache

In a cache with byte addressing, the byte you want to load is selected using the block offset. But what if I execute a LW instruction and don't want a single byte but a full 32 bit word? Is there ...
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1answer
68 views

Difference between system bus, address bus and data bus?

What is the difference between system bus, address bus and data bus? Are they different wires or they are using same wires but logically different?
1
vote
1answer
35 views

How is a 2-bit predictor better than a 1-bit predictor at determining loop iterations

I have read various explanations why a 1-bit branch predictor is wrong twice per loop, once at the beginning when it wrongly predicts against entering the loop and once at the end when it wrongly ...
1
vote
1answer
25 views

Flags register in an out-of-order processor

LW R2, 0(R1) CMP R3, R2 CMP R7, R5 the LW instruction stalls the first CMP so the second one will execute first. Wouldn't this cause the flags register to contain ...
0
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1answer
38 views

What's the difference between a reorder buffer and an instruction window?

In an out-of-order processor, what is the difference between a reorder buffer and an instruction window? Wikipedia says: "In particular, in a conventional design, the instruction window consists of ...
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1answer
42 views
1
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1answer
68 views

What is happening in this part of the LC3? [closed]

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...
3
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3answers
192 views

How was the ALU implemented in the first computer (i.e., Babbage's analytical engine)?

I've seen circuit level implementations of ALU's before, but how are NOT/AND/ADD performed mechanically?
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0answers
46 views

Which of the following instructions can reference a memory location that is #1000 locations from the instruction?

I am working on a question from a practice computer organization exam. The answer key to one of the questions says that both LD and ...
0
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2answers
82 views

Memory access on byte/word addressable memory [duplicate]

I'm doing a question on architecture and I've come across this question which I do not understand how to answer the question. Q. How many bits are required to address 4G x 32-bit main memory if a) ...
2
votes
1answer
65 views

What is this trapezoid-shaped logic component?

This is from http://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/Ch05.pdf , slide 9. From this diagram, I recognize 0001 as the opcode, which corresponds to the ADD instruction. I recognize 011, ...
0
votes
1answer
40 views

How does cpu fetch active program data (using virtual address) from storage when there is a page fault?

I read that cpu generates virtual address and using the same mmu translates to physical address and then fetches the data from RAM. But when there is a page fault, the data is fetched from the HDD(or ...
2
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0answers
37 views

Future register file in computer architecture

Results from the execution units are written into the future file when they complete (may be out-of-order). Upon operand fetching, you fetch from the future file and not the architectural register ...
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votes
1answer
50 views

Can I overcome cache coherence in coding? [closed]

I know that cache coherence is the consistency of shared resource data that ends up stored in multiple local caches. Can any programming languages handle this problem? If so, how?
0
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0answers
32 views

Calculating Effective CPI when using write-through/write-back architecture

So I'm trying to understand a homework problem given by an instructor and I'm honestly lost - I understand the concept of write-through/write-back but, I can't figure out the actual calculations ...
1
vote
1answer
111 views

Calculating the Transfer Time for a Hard Disk

I know that transfer rate is data size over transfer speed - but according to the information given, I don't know what the data size is to calculate the transfer rate. Am I missing something or was I ...