Organization and design of computer hardware.

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Translating a logical address into a physical address [on hold]

There is a logical address 87536 which needs to be translated into physical address. Here is the page table Page table:(page # - Page Frame #) ...
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What are the minimum memory requirments a microprocessors must have to perform any calculation?

Please excuse my ignorance in low level things. A lot of the written below might be very wrong. As far as I understand (and I might be very wrong), there are two types of memory locations a ...
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What is the signal going from the computer to the screen? [closed]

Im sorry if it is a weird question, but I cant seem to find an answer for this. What does the signal going to the screen look like in more abstract sense? Does it code the values of each pixel in a ...
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1answer
24 views

Explanation of Tag, Index, and Offset in Direct Mapping Cache

I'm going through an exercise trying to store address references into a direct mapped cache with 128 blocks and a block size of 32 bytes. The address are 20000, 20004, 20008, and 20016 in base 10. ...
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Computer resource under-usage [closed]

here is a list of the core components of my Dell computer: Processor: dual core Intel(R) Xeon(R) CPU E5-2630 0 @ 2.30GHz RAM: 96 GB System: Windows 7 64-bit Hard drives: 2TB SATA Video: NVIDIA Quadro ...
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Addressing modes [migrated]

I have some basic questions about addressing modes in Assembly. I'm given the following instruction: mov 3[R2+], 0x100 , where the first operand, given in index addressing mode, is the ...
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1answer
47 views

Why aren't there computers with a base different than 2? [duplicate]

Wouldn't non-digital computers, those that use a base higher than 2, be faster and more efficient? Especially with Moore's law reaching its limit, wouldn't circuits that have three, four or five ...
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1answer
61 views

Advantages and disadvantages of microcoded vs hardcoded architectures [closed]

Preamble I can't understand what are the advantages and disadvantages of microcoded processor architecture and hardcoded one. Basically what I understood is that a microcode architecture divides an ...
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1answer
15 views

Is running AES NI in parallel possible (one encryption per core/thread)?

AES NI seems to perform AES operations much faster than doing in software. However, if I have a machine with a large number of cores (say 32 cores), can I perform 32 AES encryptions using AES NI ...
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2answers
76 views

Why are computers so complicated? [closed]

I'm not sure this is on-topic or even the right website, please point me in the right direction if not. I was wondering why computers are so incredibly complex. This question is as naive as it ...
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1answer
95 views

Calculating miss rates of word-addressable and direct-mapped cache

This a problem in a computer architecture course that's giving me some trouble: You have an application whose memory access pattern is a stream and its entire data set is 128kB. The data cache in ...
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Additional clarification about Simultaneous Multithreading

I was looking for comments about SMT and got several responses. The last one looks strange: Simultaneous multithreading, which can only be implemented on a multicore system, executes the ...
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67 views

Superscalar processors and complex instructions

I read that a supercalar processor has redundant functional units. One can read this e.g. on Wikipedia. How do such redundant units work? Is a complex instruction (for accelerating heavy process, ...
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2answers
62 views

Why did MIPS include shamt and distinguish funct/opcode?

I'm confused as to why the MIPS designers would include 5 bits dedicated to shifting and have separate opcode and function bits. Because MIPS is so RISC I assume that only shifting would be done in ...
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2answers
37 views

What is a good design for expanding opcodes?

Are there any tutorials on YouTube or good text tutorials on designing expanding opcodes? I always make mistakes on switching from one line to another and "counting" in binary. I pretty much know how ...
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3answers
503 views

Moore's law and Clock Speed

This figure says according to moore's law number of transistors doubles about two years. but clock speed, power flattening after given stage. can anyone describe the reasons this flattening in ...
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3answers
341 views

Is a supercomputer more powerful than the total of all the world's computers in 2004?

The supercomputer I am researching has 2.2 petaflops and boasts total memory of 1000 terabytes and disk space of 23.5 petabytes. Is this more computing power than the total of the entire worlds ...
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2answers
54 views

Why do Computers use Hex Number System at assembly language?

Why do computer use Hex Number System at assembly language? Why don't they use any other number system like binary, octal, decimal? What thing forced computer designer to use hex system at assembly? ...
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Why Do Computers Use the Binary Number System (0,1)?

Why Do Computers Use the Binary Number System (0,1)? Why don't they use Ternary Number System (0,1,2) or any other number system instead?
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What are current cache algorithms and cache strategies?

Which cache strategies/algorithms (especially for L2 Cache) are used in practice and don't exist solely in research/theory? There is a list on Wikipedia which does not state which algorithms are ...
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1answer
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Counting the number of instructions in an instruction set

An imaginary processor has the following hardware specification: 8bit data bus 12bit address bus 32 × 8bit general purpose registers e.g. S0 – ...
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Need help with a set-associative cache memory problem

I'm studying for my Computer Architecture exam next week, and I'm having problems understanding how a set associative cache works and how to solve related problems like this one : "A set-associative ...
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1answer
60 views

Are cache contents specific to a process?

Suppose the L1 cache is filled up with data from some process. Now CPU loads another process. Does the new process share cache contents? Or the cache has to be invalidated completely in each context ...
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Can the end-to-end principle be formalized?

In the late 1990s, when I was in graduate school, the paper JH Saltzer; DP Reed; DD Clark: End-to-end arguments in system design. ACM Trans. Comput. Syst. 2(4):277-288, 1984. ...
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62 views

Is it possible to accurately determine the number of instructions required to multiply or add two integers in a modern processor?

I'm not nearly at the experience level in computer science to be able to properly determine the number of instructions involved in basic ALU calculations, and I'm interested in a certain software ...
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What are the treatises on how to build mechanical computers?

I've just watched this replica of the Antikythera mechanism. I've heard also about Babagge's analytical machine and the Curta calculator. I got curious: What did they use to build computers made of ...
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Which architecture do modern computers use?

Is it one of: Harvard Modified Harvard von Neumann Or are they antiquated models that modern computers are only loosely based on? If you asked Intel or AMD what would they say?
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1answer
53 views

Why do servers use ECC memory? [closed]

I understand that ECC checks for errors and corrects them automatically without the knowledge of the operating system or user. I don't understand however why servers often use ECC memory?
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Simultaneous execution on a Von Neuman architecture

I have a CS course at Uni. Had an exam about two last week with a question I did not get, but still, am not totally comfortable with the expected answer. Basically, we were asked Many processes ...
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1answer
45 views

Computer Architecture - Von Neumann

With regards to introductory (beginner) Von Neumann computer architecture, how does a program change the order in which instructions are executed? I know the control unit is responsible for ...
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Is there anything lower than the bit level of 1s and 0s?

When learning about the architecture of computers and how it works, we are thought that the lowest language that we can find that the machine understands is binary as 1&0. And anything that we ...
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1answer
48 views

Which kind of interrupt has the highest priority on 8086 processors? [closed]

Which of the following interrupts has the highest priority in 8086 micro-processor: Overflow, NMI or Type 255? The book I read suggests that type 255 has highest priority. But most of the searches ...
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1answer
45 views

Is my understanding of kernels correct?

System: Application OS: Scheduler, VMM, IPC, FS Drivers, dispatchers, VFS The above would be a monolithic kernel. In a monolithic kernel all core OS functions are separate from user spaaaaaace. ...
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Branch Prediction - LOCAL BHR without tag

I have a question about the common course "Computer Architecture". How is it possible to have a LOCAL Branch Predecitor with 1024 entries, 3 bits for HISTORY but without a TAG. As I understand,in ...
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Memory latency, bank busy time and stride in vector architecture

The question I ask is in reference to the Appendix G of Hennessy Patterson 4th Edition computer architecture book. On page G-23, it is written that if there are 64 memory banks and the stride is 32 ...
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3answers
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Does exploiting a spatial Locality in Cache always leads to a lower miss rate?

I've read that, incorporating many words(spatial locality) per cache blocks leads to lower miss rate. Is it the case always? One possibility of such approach is to make a single cache block of size ...
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Why does x86 has explicit register definitions, and RISC's doesn't?

For example, on x86, we have a set of general registers, each named to the function it carries out. We have an Accumulator, which is a storage for a results of different fixed point operations, we ...
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Heterogenous and Asymmetric Computing's differences

The definition of the both architecture looks pretty same. They are parallel computing architecture with different type of cores. What distinguish their definition, actually?
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MIPS: sign extend in I-Type commands

My lecturer told me that when I use an arithmetic I-Type command (ADDI,SUBI etc.) , the IMM field gets sign extended, and when I use a logic I-Type command (ORI,ANDI etc.) , the IMM field is just ...
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Critical path of MIPS single cycle CPU

I'm doing the exercises from "Computer Organization and Design, Fourth Edition: The Hardware and Software Interface" by David Patterson and John Hennessy. I've come across a problem that states: ...
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Why does a processor have 32 registers?

I've always wondered why processors stopped at 32 registers. It's by far the fastest piece of the machine, why not just make bigger processors with more registers? Wouldn't that mean less going to the ...
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A question from Computer Organization on Peak Clock Frequency

Given below are 3 different pipelined processors: $P_1:\ 4\ stages\ with\ delays\ \ \ \ 0.6_{ms}\ \ 0.8_{ms}\ \ 0.6_{ms}\ \ 1.1_{ms}\\ P_2:\ 4\ stages\ with\ delays\ \ \ \ 2.0_{ms}\ \ 1.8_{ms}\ \ ...
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Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
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Execution time of an uneven pipeline

I was trying to solve a question dealing with n instructions in an uneven pipeline with k stages. I came across a generic formula for even pipelines i.e. (k + n - 1) * clock cycle. But I feel this ...
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1answer
77 views

What happens at the decode phase of the instruction cycle?

I am reading about the various phases of the Instruction Execution, I found out that we have three phases like below. Fectch Decode Execute Now if the part I don't understand is why do we need a ...
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branch prediction buffer - 5 stage integer MIPS [closed]

will you recommend use of branch prediction buffers for 5 stage integer MIPS pipeline. Does this increase the efficiency or not?
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MIPS Architecture : PC-relative addressing [duplicate]

In case of branch Instructions such as beq, bne, we use PC-relative addressing. But I am not clear why it is said in most of the ...
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2answers
112 views

MIPS Architecture : PC-relative addressing

In case of branch Instructions such as beq, bne, we use PC-relative addressing. But I am really not clear why it is said in ...
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Is there any defined programming model for 'Self-Learning' NPUs?

Qualcomm is creating a Neuromorphic Processing Unit or an NPU called zeroth. IBM is also working on a brain inspired chip under Synapse program. Standford's Neurogrid might be a similar example. ...
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Why do we need so many transistors in a chip, and how are they managed?

My knowledge is very vague as all we have are visual diagrams etc, but we have memory address and registers, the ALU being the heart(apparently). Single core CPUs process one instruction at a time ...