Questions about the organization and design of computer hardware.

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what is the difference between memory access and data memory access?

what is the difference between memory access and data memory access? for example, here are the examples of register transfer language instructions: $R1 ←[18]$ $R2 ←[R1 +3]$ $R1 ← R1 ...
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Is it possible to Expand the RAM memory of Laptop using cloud? [on hold]

is it possible to expand the RAM memory of laptop using Cloud??? if yes den vl it be harmful to laptop??
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0answers
30 views

Applying information theory to processor clocks

Has there been any research on the subject of applying information theory to a processors clock? It occurred to me that a clock is actually transmitting data that is used for synchronization of ...
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1answer
27 views

Data interchange in two registers

This picture is from Computer System Architecture 3rd Edition by Morris Mano. Is it possible to interchange the data of any two registers in a single clock pulse? I know that the data of DR (data ...
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0answers
15 views

Average Time for Write Through & Write Back policies

Tc -> cache updation time(per word) Tm -> main memory updation time(per word) Tb -> updation time of a block (Both policies below don't follow a strict hierarchy. i.e. if there is a miss the ...
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2answers
85 views

Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
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2answers
48 views

Computer cache - data removing

I am programming CPU cache simulator and I am supposed to implement removing of entries. I will not use LRU but just random. I am not really clear, when should I call the removing function? When ...
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1answer
44 views

programs compatible with different processors

Ok, I've been told for years that during the old days, a program written on a certain machine would run only on that machine but now, programs run on multiple types of computers. What does this ...
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1answer
38 views

How does the CPU know to get data from or send data to a peripheral device?

We were talking today, in Intro to Programming, about machine language. I know it's a bunch of 0's and 1's. Let's say I compile the following C++ program on an x86 machine: ...
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18 views

Understanding Computer organisation and architecture [closed]

What are some of the books for "computer organisation and architechture" which are best for self study. Such a text that one can grasps the big picture, and understandhow various things are fitting ...
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1answer
20 views

Why is c) a combinational circuit, but d) not?

I am doing practice after just learning what combinational circuits are, yet I am unsure of why (c) is combinational, but (d) is not. Can someone please explain to me why this is? The Solution ...
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27 views

Possible results of two programs running on a symmetric multicore system

This question is from Patterson and Hennessy's Computer Organization and Design. Consider the following portions of two different programs running at the same time on four processors in a ...
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0answers
18 views

What are exceptions and how they will be raised in pipeline

Hi I am not sure what is exception here and how it will be raised in following case Sub $11,$2,$4 And $12,$2,$5 Or $13, $2,$6 Add $1,$2,$1 Slt $15,$6,$7 I was ...
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2answers
44 views

Does having one large L1 cache instead of L1 and L2 cache makes computation faster?

Does having one larger L1 cache instead of L1 and L2 cache makes computation faster? Also will this make the CPU more expensive to make?
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1answer
60 views

Relation between hardware and software [closed]

I'm very interested in computing and programming. I have done a lot of programming with different languages although I have a question nobody was able to answer until now. I question myself how is ...
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0answers
27 views

Which is faster operations on register operands or immediate operands?

I am reading the book Computer Organization and Design. It compares instructions on memory and instructions on registers but doesn't say anything about the speed of instructions when the source ...
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1answer
55 views

Scheduling distributed computational graph

I work in computational fluid dynamics. And I spend most of my time waiting for simulation to complete. The common way to improve simulation performance is to use a suitable distributed linear ...
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1answer
27 views

Where is the reorder buffer (ROB)? [closed]

I just wonder where the ROB is in. Is ROB in the memory or cache or where??
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1answer
70 views

Relationship between RAM size and 32-bit vs 64-bit word size

I know that x86 supports only 4GB of RAM, and that switching to x64 greatly increases the size of RAM you can use, but I don't understand why. Why is the maximum supported ram size related to whether ...
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1answer
31 views

Where are the address, control and data buses on a computer

So have been reading up on data buses, address buses and control buses and I understand what they do, but am confused about where they can physically be found. Some books/sites I have found state that ...
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1answer
71 views

In a $k$-way set associative cache,main memory block mapping in range?

In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are ...
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1answer
25 views

Secondary Storage in Von Neumann Achitecture

For an assignment, I need to draw a diagram of Von Neumann architecture, and explain each part of it. All the diagrams and explanations I've seen have a distinct "Memory" block that holds both the ...
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1answer
107 views

Which addressing modes permits relocation without any change whatsoever in the code?

An exercise problem stated that : Which of the following addressing modes permits relocation without any change whatsoever in the code? Indirect addressing Indexed addressing Base register ...
2
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3answers
84 views

How is clock syncing implemented?

I'm looking for an explanation or reference on the implementation of computer clock. To keep the question at the level of logical abstractions: say, we put together some combinational and sequential ...
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2answers
61 views

CISC and RISC - synchronous and asynchronous

I have two opposing ideas. I think that all the instructions in a RISC take the same time what makes me believe RISC is associated with synchronous. At the same time i think that CISC should be ...
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1answer
250 views

Difficult Question to Understand (Computer Artitechture) [closed]

You are designing an elevator controller for a building with 25 floors. The controller has two inputs: UP and DOWN. It produces an output indicating the floor that the elevator is on. There is no ...
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2answers
203 views

Is word size, the size of a memory location? the size of the data bus? or the cpu register size?

Is word size, the size of a memory location? the size of the data bus? or the cpu register size? Suppose you have a computer, memory address #0 has byte AB memory address #1 has byte F3 memory ...
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0answers
78 views

Converting SRAM to another SRAM [closed]

How would I convert a 16K x 32 SRAM into a 64K x 8 SRAM? The 16K x 32 RAM module is a single unit that cannot be altered internally and is capable of address decoding, has tristate outputs, and ...
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1answer
25 views

Feasible to apply image “interlacing” concept to video streaming for smoother buffering?

The current state of video buffering technology is to encode a video multiple times at different resolutions, then when your network speed changes you change which video you are buffering from. Would ...
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0answers
44 views

How to design a simpler Version of CARDIAC (Cardboard Illustrative Aid to Computers)?

I'm trying to make a simpler version of CARDIAC for only performing addition. Now, I am encountering several problems in making something similar and looking for some ideas (I'm new to Computer ...
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2answers
114 views

Why can we not read and write to the same address at the same time?

I was reading Wikipedia about the von Neumann bottleneck. Surely there is some simple answer to this. Why can we not read and write to the same address at the same time? We can if the addresses are ...
2
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1answer
233 views

Hex Bit Pattern to IEEE 754 standard Floating Point Number

The question asks for the decimal number that 0x0C000000 represents if it is a floating number. I'm not too sure on how to approach this, but here's my thought process: 0x0C000000 = 0000 1100 0000 ...
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0answers
49 views

Recommendation book to learn how computers work at a transistor level [closed]

I would like to know your book recommendations / popular books to learn how computers perform operations, store memory, process your mouse input to open a program for example (maybe not that ...
2
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1answer
122 views

Read After Write(RAW) hazard

I am confused in finding RAW dependencies whether we have to find only in adjacent instructions or non-adjacent also. consider the following assembly code I1: ADD R1 , R2, R2; I2: ADD R3, R2, R1; ...
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1answer
38 views

Does the databus size matter for determining the range of the memory addresses?

If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory? E.g. : Assume a 32-bit word. If you have ...
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2answers
62 views

Can the memory cache hold instructions?

My teacher told us that when the ram runs out of space it will push a program in the cache, i argued that the program should go to the swap space in the hard drive, plus the memory cache cannot hold ...
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10answers
5k views

If the speed of electrical charge hasn't changed, how have computers become faster?

Everyone knows computing speed has drastically increased since their invention, and it looks set to continue. But one thing is puzzling me: if you ran an electrical current through a material today, ...
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0answers
129 views

Are CPU architectures biased towards procedural runtimes?

Are there any changes that could be made to CPUs to make them perform better for concurrent runtimes like Rust? For instance, are there changes to branch prediction implementations or cache sizes ...
2
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1answer
109 views

How can i compute tag-index-displacement bits of an address if cache size is not a power of two?

How can i compute tag-index-displacement bits from an address if cache size is not a power of two? Intuitively, i would be inclined to think that i can not directly indicate which bits of the address ...
2
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1answer
119 views

What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...
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1answer
147 views

Will ternary computers be faster than binary? [duplicate]

If we had a computer in base 3 which used the characters {0, 1, 2} instead of just {0, 1} (and we implemented a ternary logic on ...
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9answers
4k views

Is a universal assembly language for all computers possible?

I would like to ask a few questions about Assembly language. My understanding is that it's very close to machine language, making it faster and more efficient. Since we have different computer ...
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3answers
166 views

Why don't computers use the same architecture?

We just started on the Computer Architecture topic in our CS lectures and I have a few questions that are currently bothering me. So we have different computers, and there are always differences in ...
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4answers
117 views

How are alphabetic characters programmed into a computer?

I'm no cs student, I'm a programmer. I have a couple of questions and a few assumptions that I will make here (correct me if I'm wrong please). From my understanding is that all the sequences of 1 ...
2
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1answer
773 views

Differences between SISD, SIMD and MIMD architecture (Flynn classification)

I have a problem with classifying certain CPUs to the proper classes of Flynn's Taxonomy. 1. Zilog Z80 According to this article on Sega Retro, Z80 has limited abilities to be classified as SIMD: ...
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0answers
29 views

Two versions of arithmetic instructions in RISC. One modifies the flags and the other doesn't [duplicate]

I've read that in RISC architecture most arithmetic instructions have two "versions": one that modifies the flags after calculations one that doesn't modify any flags. My question is: why is it ...
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2answers
214 views

How to calculate the size of a page in a two level paging CPU?

I am having difficulties with understanding the concept of paging. As a result I've got no idea how I can solve the following exercise - I'm lacking one more equation to solve it. I've read a lot ...
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4answers
166 views

Can only information(data) be stored in ram?

Basic question, but is only information/ data stored in ram? Are computer files such as a word file considered information/ data? This is one of the questions in a summer assignment for ap computer ...
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1answer
70 views

2-core 2.6GHz vs 4-core 1.3GHz [closed]

If a process could run as much cores as available, which CPU is faster, a 2-core 2.6GHz CPU or a 4-core 1.3GHz CPU?
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1answer
56 views

Can the processor just turn off the interrupt request line?

I was doing some of the interrupts question online and found this Multiple choice question How can the processor ignore other interrupts when it is servicing one a) By turning off the interrupt ...