Questions about the organization and design of computer hardware.

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What factors influence machine epsilon?

I was wondering what factors effect a machine's epsilon value. I was thinking about how modern computers can calculate expressions to higher accuracy then their predecessors, but what hardware and ...
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26 views
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63 views

Fundamental idea of this memory denial of service simulation using array copy?

I am just watching this lecture Computer Organization - Introduction And Basics where the lecturer mentions about using a simple code to demonstrate how memory denial of service can be simulated in ...
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12 views

Share PDF files with permissions [closed]

in my office we share PDF Files company wide via email but they have to email us back to say who they're sending the PDF to. Is there a way to automate this process maybe using an online hosting ...
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17 views

Which combination of the following features will suffice to characterize an OS as a multi-programmed OS

Which combination of the following features will suffice to characterize an OS as a multi-programmed OS? More than one program may be loaded into main memory at the same time for execution. If a ...
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3answers
2k views

A multi-user, multi-processing operating system cannot be implemented on hardware that does not support

A multi-user, multi-processing operating system cannot be implemented on hardware that does not support Address translation DMA for disk transfer At least two modes of CPU execution (privileged and ...
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269 views

Why the Smallest Operable Data Type in Most Programming Languages Is One-Byte Sized? [duplicate]

Why the smallest operable data type in most programming languages is one-byte sized? Is it possible that to operate with a single bit? If it is possible, how to do it in practical?
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2answers
528 views

Would removing the branch delay slots change the instructions set architecture?

I am trying to study for an exam and I noticed a lot of the questions follow the idea of "Changing the ISA". From my understanding the ISA dictates the structure and format of instructions, so ...
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20 views

TAG dimension in Direct Mapping and N-way associative

someone can help with this quiz: 1) We have a direct mapping cache memory with 2^10 lines. Each line is hosting 32 data. How many bits are necessary for the TAG for a 24 bits address bus? 2) We ...
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12 views

Advice on using DRAMSimm2 or other DRAM simulation tools

As part of my PhD research I am currently building a simulation of a 256 core NoC and really want to model its interaction with the memory system. My supervisor has suggested using the University of ...
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1answer
28 views

RISC machines have register renaming?

I know that one of the techniques used by RISC machines to improve the pipeline is the delayed branch, but what other techniques do they employ, namely, can they use register renaming? I know that ...
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2answers
26 views

What does the number of bit of microprocessor mean?

Intel 8085 is a 8 bit processor whereas 8086 is a 16 bit processor,what does the number of bit specify?
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50 views

Pros and Cons of Average Memory Access Time When Increasing Cache Block Size

Assuming we have a single-level (L1) cache and main memory, what are some of the advantages and disadvantages of having a larger cache block size (considering average memory access time). The only ...
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1answer
51 views

What exactly (and precisely) is “offset”?

Just like my previous question concerning 'hash'; what exactly is an (or the) "offset?" Is it a value or data type? Or is it an address location? I have heard it used in different contexts within the ...
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1answer
50 views

Questions about SIMD instructions

What is the trend over time for the size of registers of x86 CPUs? I know that we have today 512-bit registers, but is there a kind of Moore's Law to predict the size of registers in the future? ...
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2answers
293 views

How Is a Computer Able to Store and Quickly Manipulate All the Data Required For A Computer Display?

I did some quick math on how much data is contained on a screen at any given instant and I ended up with a number well beyond what I thought was possible. 256 colors for Red, Green, and Blue each ...
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2answers
35 views

Is it possible to construct 3-dimensional microchips?

In our daily computer, the microchips in it are 2-dimensional, but could it be possible to produce 3-dimensional ones, in some way similar to the brain structure?
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1answer
36 views

Convert non-integer decimal to octal

I follow a course in Computer Architecture and I'm making exercises on number conversions. Now one of the questions asks me to convert 251.5625 to octal and hexdecimal base. No further info is given. ...
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1answer
26 views

In instruction pipelining, can we forward an operand more than one clock cycle?

Most operand forwarding examples that use the standard 5-stage MIPS pipeline forward operands from EX or MEM by ONE clock cyle to a later instruction. Is it possible to do so for more than one (from ...
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1answer
45 views

How did early computers handle variable word length?

So quoting from the book: A History of Modern Computing (History of Computing) The introduction of reliable core memory made it practical to fetch data in sets of bits, rather than one bit at a ...
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1answer
114 views

D - Latch or D Flip Flop?

I have a diagram (http://imgur.com/cET8Q14) where it is either a D Latch or D Flip Flop. I am trying to figure out which one it is and why. If it is a D Flip Flip, I also need to know which input is ...
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1answer
59 views

Depth of a pipeline in a CPU's architecture

I follow a course on CPU architectures and I'm making exercises at the moment. Now I encountered the word "depth of a pipeline" in one of the exercises, but I don't know what's meant by the depth of a ...
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2answers
86 views

How likely is it that a computer miscalculates 1+1? [closed]

Of course, normally a fully-functional computer will calculate 1+1=2. However, the physics governing the behavior of a chip is quantum mechanical. So in principle there is a certain probability that ...
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1answer
58 views

What does it mean that a core supports 2 threads?

I understand that a process may have multiple threads, and that a processor may have multiple cores to run processes in parallel. But I can't understand how a core may allow multiple threads, what ...
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9 views

how to track a uop's flag in microprocessor?

Lots of processor renaming their register to achieve the goal of out-of-order,but how to track the instruction's flag,such as carry flag,overflow flag,etc?
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3answers
144 views

CPU and GPU differences

What is the difference between a single processing unit of CPU and single processing unit of GPU?  Most places I've come along on the internet cover the high level differences between the two. I want ...
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26 views

Is this Von Neumann Architecture Diagram Correct?

I am preparing for an Exam and would like to know whether this diagram of the Von Neumann Architecture is correct or not. The full form of the acronyms (on the diagram) are as follows: PC: Program ...
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33 views

How to show potential pipeline hazards

Based on following table, I have to show if there is any potential pipeline hazard in the following code segments: X = R2 + Y, R4 = R2 + X R1 = R2 + X, X = R3 + Y, Z = R1 + X. I've been a ...
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18 views

Miss penalty for Write request in a Write-Back style system

If the processor is trying to write a word to a certain memory location, and the system uses a write-back style architecture, what happens in case of a miss? I'm assuming that the system would first ...
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1answer
78 views

How does CPU actually retrieve data from memory when you call a variable in a programming language?

As I have understood from all the internet sources I can get to, when you declare and initialize a variable in java, you are allocating this data, say an 8-byte float, in a particular memory cell in ...
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18 views

Draw the Logic Diagram using Half-Adders to implement a ripple-carry addition for the increment

Draw the Logic Diagram using Half-Adders to implement a ripple-carry addition for the increment.(Designing the incrementer circuit for the picture below) Having a tough time drawing out this logic ...
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22 views

Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
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1answer
46 views

Is emulation and/or virtualization faster when the host and guest systems are more similar?

Is emulation and/ or virtualization performance faster when the guest and host OS are similar? If yes, how big, relatively speaking, is the difference? And whether the answer is yes or no, why is it ...
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1answer
105 views

Computing the hit and miss ratio of a cache organized as either direct mapped or two-way associative

This is an example problem in a computer organization and architecture course that's giving me some trouble. It goes as follows: Consider a cache of 4 lines of 16 bytes each. Main memory is ...
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1answer
42 views

How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, DeviceByLogicalSector(50)...
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31 views

How is parallel tag checking achieved in associative Mapping?

I originally posted this question on stack overflow and then realised it was better suited to computer science . In the book on computer organization and architecture by William stallings , in the ...
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3answers
4k views

How do computers keep track of time?

How are computers able to tell the exactly correct time and date every time I switch it on? Whenever I close the computer (shut it down) all connections and processes inside stop. How is it that ...
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Lazy way of comparing ISA on code length

I hope this is not too broad. I need to evaluate about 8 different ISA targets for about 12 specs. The only metric I'm intersted in is size of the output bytecode. Moreover, I'm only interested in ...
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1answer
60 views

Mano base computer and the FGO flag

I have a question about the Mano base computer. The state diagram, shown below, implies that the output device will set the FGO flag to "1" after the job is done to continue the output activity from ...
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1answer
43 views

For what $N$ does $2^N$ overflow?

Consider the following computation: 2^N (TWO TO THE POWER OF ‘N’, for Int. N>0), being executed on a processor with 32 bit internal, user and ALU registers. The registers rightmost bit is bit 0 and ...
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64 views

Difference between capacity miss and conflict miss

Premise: Two types of cache miss: capacity miss, conflict miss\ Cache contains only 2 sets, SET 1 and SET 2 Problem: If data A maps to SET 1 and it doesn't exist in SET 1 while SET 1 is fully ...
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1answer
68 views

Is there a CPU architecture which allows early register access?

In Intel's x86 architecture, imul (integer multiply) usually has latency of a few clock cycles. Those CPUs are very smart in filling the time (e.g., pipelining or out-of-order execution), but do any ...
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1answer
60 views

Universal memcomputing machines (UMM)

This paper on memcomputing seems like a really big deal, but it doesn't seem to be particularly popular. They prove that their UMM can solve NP problems in P, although they don't claim P = NP. In ...
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37 views

Performance on modifying cycle time

I learnt in my computer architecture course on Caches, that if we keep the memory speed of a machine the same and half the clock cycle time, the miss penalty doubles. Why does this happen? What is ...
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1answer
41 views

How does a register remember value?

So I am studying this great book, and Chapter $3.1$ is about registers. Quoting from this book / chapter: A register is a storage device that can "store" or "remember" a value over time, ...
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54 views

Why is word-addressable the exception, not the rule?

As stated on Wikipedia: Most modern computers are byte-addressable instead of word-addressable. Why is this case? Since the CPU processes words (of predominantly 64 bits or 8 bytes) now, wouldn'...
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80 views

what are read/write operations involved in main memory, cache and processor?

please bear with me, I always get confused with the terminologies used in my computer architecture class. What are read and write operations exactly? What are their relationship with processor, main ...
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31 views

What the length of instructions on these processors will be?

Let's say we have two computers with identical ISA, but different size of word in main memory. One is 32 bit and the other 64 bits. So will it be identical length of instruction, different, depends on ...
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74 views

Number of processes needed to maximize CPU utilization under I/O wait conditions

A computer has 2 GB of RAM of which the operating system occupies 256 MB. The processes are all 128 MB (for simplicity) and have the same characteristics. If the goal is 99% CPU utilization, what is ...