Questions about the organization and design of computer hardware.

learn more… | top users | synonyms

0
votes
2answers
18 views

Is it possible to construct 3-dimensional microchips?

In our daily computer, the microchips in it are 2-dimensional, but could it be possible to produce 3-dimensional ones, in some way similar to the brain structure?
1
vote
1answer
26 views

Convert non-integer decimal to octal

I follow a course in Computer Architecture and I'm making exercises on number conversions. Now one of the questions asks me to convert 251.5625 to octal and hexdecimal base. No further info is given. ...
2
votes
0answers
13 views

In instruction pipelining, can we forward an operand more than one clock cycle?

Most operand forwarding examples that use the standard 5-stage MIPS pipeline forward operands from EX or MEM by ONE clock cyle to a later instruction. Is it possible to do so for more than one (from ...
1
vote
1answer
42 views

How did early computers handle variable word length?

So quoting from the book: A History of Modern Computing (History of Computing) The introduction of reliable core memory made it practical to fetch data in sets of bits, rather than one bit at a ...
-3
votes
1answer
52 views

D - Latch or D Flip Flop?

I have a diagram (http://imgur.com/cET8Q14) where it is either a D Latch or D Flip Flop. I am trying to figure out which one it is and why. If it is a D Flip Flip, I also need to know which input is ...
2
votes
1answer
40 views

Depth of a pipeline in a CPU's architecture

I follow a course on CPU architectures and I'm making exercises at the moment. Now I encountered the word "depth of a pipeline" in one of the exercises, but I don't know what's meant by the depth of a ...
3
votes
2answers
85 views

How likely is it that a computer miscalculates 1+1? [on hold]

Of course, normally a fully-functional computer will calculate 1+1=2. However, the physics governing the behavior of a chip is quantum mechanical. So in principle there is a certain probability that ...
0
votes
1answer
37 views

What does it mean that a core supports 2 threads?

I understand that a process may have multiple threads, and that a processor may have multiple cores to run processes in parallel. But I can't understand how a core may allow multiple threads, what ...
-4
votes
1answer
20 views

Expresse as multiples of general purpose

Honestly, I'm really ashamed of what I'm going to ask, but I don't have other choice. My teacher assigned me this task where I have to convert numbers. Thats ok, but then for the last column he told ...
0
votes
0answers
9 views

how to track a uop's flag in microprocessor?

Lots of processor renaming their register to achieve the goal of out-of-order,but how to track the instruction's flag,such as carry flag,overflow flag,etc?
5
votes
3answers
125 views

CPU and GPU differences

What is the difference between a single processing unit of CPU and single processing unit of GPU?  Most places I've come along on the internet cover the high level differences between the two. I want ...
0
votes
0answers
20 views

Is this Von Neumann Architecture Diagram Correct?

I am preparing for an Exam and would like to know whether this diagram of the Von Neumann Architecture is correct or not. The full form of the acronyms (on the diagram) are as follows: PC: Program ...
0
votes
0answers
26 views

How to show potential pipeline hazards

Based on following table, I have to show if there is any potential pipeline hazard in the following code segments: X = R2 + Y, R4 = R2 + X R1 = R2 + X, X = R3 + Y, Z = R1 + X. I've been a ...
0
votes
0answers
13 views

Miss penalty for Write request in a Write-Back style system

If the processor is trying to write a word to a certain memory location, and the system uses a write-back style architecture, what happens in case of a miss? I'm assuming that the system would first ...
2
votes
1answer
44 views

How does CPU actually retrieve data from memory when you call a variable in a programming language?

As I have understood from all the internet sources I can get to, when you declare and initialize a variable in java, you are allocating this data, say an 8-byte float, in a particular memory cell in ...
0
votes
0answers
16 views

Draw the Logic Diagram using Half-Adders to implement a ripple-carry addition for the increment

Draw the Logic Diagram using Half-Adders to implement a ripple-carry addition for the increment.(Designing the incrementer circuit for the picture below) Having a tough time drawing out this logic ...
2
votes
0answers
16 views

Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
0
votes
1answer
42 views

Is emulation and/or virtualization faster when the host and guest systems are more similar?

Is emulation and/ or virtualization performance faster when the guest and host OS are similar? If yes, how big, relatively speaking, is the difference? And whether the answer is yes or no, why is it ...
0
votes
0answers
24 views

Computing the hit and miss ratio of a cache organized as either direct mapped or two-way associative

This is an example problem in a computer organization and architecture course that's giving me some trouble. It goes as follows: Consider a cache of 4 lines of 16 bytes each. Main memory is ...
2
votes
1answer
38 views

How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, ...
1
vote
1answer
30 views

How is parallel tag checking achieved in associative Mapping?

I originally posted this question on stack overflow and then realised it was better suited to computer science . In the book on computer organization and architecture by William stallings , in the ...
37
votes
3answers
4k views

How do computers keep track of time?

How are computers able to tell the exactly correct time and date every time? Whenever I close the computer (shut it down) all connections and processes inside stop. How is it that when I open the ...
1
vote
0answers
16 views

Lazy way of comparing ISA on code length

I hope this is not too broad. I need to evaluate about 8 different ISA targets for about 12 specs. The only metric I'm intersted in is size of the output bytecode. Moreover, I'm only interested in ...
0
votes
1answer
58 views

Mano base computer and the FGO flag

I have a question about the Mano base computer. The state diagram, shown below, implies that the output device will set the FGO flag to "1" after the job is done to continue the output activity from ...
1
vote
1answer
42 views

For what $N$ does $2^N$ overflow?

Consider the following computation: 2^N (TWO TO THE POWER OF ‘N’, for Int. N>0), being executed on a processor with 32 bit internal, user and ALU registers. The registers rightmost bit is bit 0 and ...
1
vote
0answers
51 views

Difference between capacity miss and conflict miss

Premise: Two types of cache miss: capacity miss, conflict miss\ Cache contains only 2 sets, SET 1 and SET 2 Problem: If data A maps to SET 1 and it doesn't exist in SET 1 while SET 1 is fully ...
3
votes
0answers
44 views

Is there a CPU architecture which allows early register access?

In Intel's x86 architecture, imul (integer multiply) usually has latency of a few clock cycles. Those CPUs are very smart in filling the time (e.g., pipelining or out-of-order execution), but do any ...
1
vote
1answer
49 views

Universal memcomputing machines (UMM)

This paper on memcomputing seems like a really big deal, but it doesn't seem to be particularly popular. They prove that their UMM can solve NP problems in P, although they don't claim P = NP. In ...
0
votes
0answers
36 views

Performance on modifying cycle time

I learnt in my computer architecture course on Caches, that if we keep the memory speed of a machine the same and half the clock cycle time, the miss penalty doubles. Why does this happen? What is ...
2
votes
1answer
38 views

How does a register remember value?

So I am studying this great book, and Chapter $3.1$ is about registers. Quoting from this book / chapter: A register is a storage device that can "store" or "remember" a value over time, ...
3
votes
2answers
53 views

Why is word-addressable the exception, not the rule?

As stated on Wikipedia: Most modern computers are byte-addressable instead of word-addressable. Why is this case? Since the CPU processes words (of predominantly 64 bits or 8 bytes) now, ...
1
vote
1answer
34 views

what are read/write operations involved in main memory, cache and processor?

please bear with me, I always get confused with the terminologies used in my computer architecture class. What are read and write operations exactly? What are their relationship with processor, main ...
0
votes
1answer
29 views

What the length of instructions on these processors will be?

Let's say we have two computers with identical ISA, but different size of word in main memory. One is 32 bit and the other 64 bits. So will it be identical length of instruction, different, depends on ...
0
votes
1answer
58 views

Number of processes needed to maximize CPU utilization under I/O wait conditions

A computer has 2 GB of RAM of which the operating system occupies 256 MB. The processes are all 128 MB (for simplicity) and have the same characteristics. If the goal is 99% CPU utilization, what is ...
2
votes
0answers
57 views

Why ternary computers like Setun didn't catch on?

Why ternary computers like Setun didn't become popular despite being cheaper and more reliable than binary computers, and also having important computational advantages? We could have had cheaper ...
-3
votes
1answer
32 views

How is a human brain the same as a computer? [closed]

Which functions performed by the brain equal which parts/functions of a computer? For example, human memories are like data saved to a hard drive?
0
votes
0answers
39 views

Applying Amdhahl's Law

My Question is as below: The MIPS rating of a processor is 1000. However the processor requires at least one memory access per instruction. The memory latency of the system is 10 ns. If you are ...
0
votes
1answer
42 views

Is it possible to compute -12 (decimal) in 4 bits binary

This is what I have so far 1 1 0 0 Switch values by 2s Complement 0 0 1 1 + 1 0 1 0 0
0
votes
1answer
37 views

what is the difference between memory access and data memory access?

what is the difference between memory access and data memory access? for example, here are the examples of register transfer language instructions: $R1 ←[18]$ $R2 ←[R1 +3]$ $R1 ← R1 ...
1
vote
1answer
55 views

Applying information theory to processor clocks

Has there been any research on the subject of applying information theory to a processors clock? It occurred to me that a clock is actually transmitting data that is used for synchronization of ...
0
votes
1answer
30 views

Data interchange in two registers

This picture is from Computer System Architecture 3rd Edition by Morris Mano. Is it possible to interchange the data of any two registers in a single clock pulse? I know that the data of DR (data ...
0
votes
0answers
22 views

Average Time for Write Through & Write Back policies

Tc -> cache updation time(per word) Tm -> main memory updation time(per word) Tb -> updation time of a block (Both policies below don't follow a strict hierarchy. i.e. if there is a miss the ...
3
votes
2answers
104 views

Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
1
vote
2answers
51 views

Computer cache - data removing

I am programming CPU cache simulator and I am supposed to implement removing of entries. I will not use LRU but just random. I am not really clear, when should I call the removing function? When ...
1
vote
1answer
47 views

programs compatible with different processors

Ok, I've been told for years that during the old days, a program written on a certain machine would run only on that machine but now, programs run on multiple types of computers. What does this ...
3
votes
1answer
70 views

How does the CPU know to get data from or send data to a peripheral device?

We were talking today, in Intro to Programming, about machine language. I know it's a bunch of 0's and 1's. Let's say I compile the following C++ program on an x86 machine: ...
1
vote
0answers
22 views

Understanding Computer organisation and architecture [closed]

What are some of the books for "computer organisation and architechture" which are best for self study. Such a text that one can grasps the big picture, and understandhow various things are fitting ...
2
votes
1answer
26 views

Why is c) a combinational circuit, but d) not?

I am doing practice after just learning what combinational circuits are, yet I am unsure of why (c) is combinational, but (d) is not. Can someone please explain to me why this is? The Solution ...
0
votes
0answers
44 views

Possible results of two programs running on a symmetric multicore system

This question is from Patterson and Hennessy's Computer Organization and Design. Consider the following portions of two different programs running at the same time on four processors in a ...
0
votes
0answers
22 views

What are exceptions and how they will be raised in pipeline

Hi I am not sure what is exception here and how it will be raised in following case Sub $11,$2,$4 And $12,$2,$5 Or $13, $2,$6 Add $1,$2,$1 Slt $15,$6,$7 I was ...