Questions about the organization and design of computer hardware.

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Two versions of arithmetic instructions in RISC. One modifies the flags and the other doesn't [duplicate]

I've read that in RISC architecture most arithmetic instructions have two "versions": one that modifies the flags after calculations one that doesn't modify any flags. My question is: why is it ...
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New computer build shuting down after half second [on hold]

My build is the following : AMD FX 8320 CPU GEFORCE 750ti 2GB STRIX OC MSI 970 GAMING MOTHERBOARD 2X HYPER 4 GB RAM SATA 3.5 500GB PSU http://www.marsgaming.eu/power-supply/mp600/ All my pc ...
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doing register transfer micro operations simultaneously [on hold]

If i have the following statement: P: R2<-R1 , R1<-R2 If the binary data in R1 is 101 and the binary data in R2 is 111 . In the output will the data in the two registers be exchanged?
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computer blue screen for almost all applications [closed]

i bought a computer 7 years ago : it is a good one, especially for that time , i mean , the components are : Nvidia 9500 GT, 4 gb ram, intel dual core. BUT for some 4 years i got a problem. It ...
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4answers
88 views

Can only information(data) be stored in ram?

Basic question, but is only information/ data stored in ram? Are computer files such as a word file considered information/ data? This is one of the questions in a summer assignment for ap computer ...
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1answer
45 views

2-core 2.6GHz vs 4-core 1.3GHz [closed]

If a process could run as much cores as available, which CPU is faster, a 2-core 2.6GHz CPU or a 4-core 1.3GHz CPU?
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Can the processor just turn off the interrupt request line?

I was doing some of the interrupts question online and found this Multiple choice question How can the processor ignore other interrupts when it is servicing one a) By turning off the interrupt ...
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2answers
28 views

Bytes and bits conversion?

It is claimed in my textbook that In a 32-bit system, The instruction LDR r4,[r6] lets you address a logical space of 4GB. I know where the 4GB comes from, It is simply 2^32 / (1024 x 1024 x ...
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1answer
27 views

How does the operating system set up memory boundaries? [closed]

Is there a hardware interrupt that is pre-configured by the OS or something? Try to keep the answer on the scale of a register or so. Are some special preparatory signals sent across the bridges ...
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How can the OS use interrupts and regain control from another process? [duplicate]

I read on the wikipedia page that the interrupt handler uses a jump table or something, at least for software, but how does the OS set up interrupts so that execution comes back to it, and how do ...
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0answers
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How does the OS regulate CPU permissions? [duplicate]

How does the operating system limit the instruction set of the CPU to other processes? I know that it'd take forever for the loader to parse out the executable code, so is there are hardware ...
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2answers
26 views

Clear interrupt instruction in a pipelined CPU

Say you execute a clear interrupt instruction (CLI) in a pipelined CPU. While that instruction is being fetched, an interrupt occurs, so the instruction after the CLI is from the interrupt handler. ...
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1answer
20 views

CPU reading cycles. [closed]

Assume the CPU has 64 data lines. Then Z reading cycles will be needed to load an array of 12 double-precision floating-point numbers, each number coded in eight bytes, from the main memory into the ...
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0answers
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Can TASM code run on NASM and vice versa? [migrated]

I'm taking a course on computer organisation and architecture and as part of the course we have to learn assembly language. They tell us to install NASM but that TASM and MASM are also perfectly ...
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2answers
52 views

Data General MV/8000 virtues of “No mode bit”

I'm reading Tracy Kidder's "The Soul of a New Machine" where a team at Data General design a new machine (codenamed "Eagle", later named MV/8000). It is 32-bit extension of a previous architecture ...
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4answers
75 views

Is there any development in continuous-value computers?

Is there anything that hints at the possibility of a (modern) continuous-value computer, since modern computers are based on discrete arithmetic? I guess the old analog computers were of this ...
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1answer
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Is the front-side bus multiplier the same as how many transfers it does per second?

What I am doing: I've been reading there about front-side busses (FSB) and their cycles per second (MHz) vs. bandwidth (Millions of Transactions per second or MT/s). What I've understood: FSB's MHz ...
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1answer
15 views

Register Transfer Activity

In a simple architecture(not considering parallel architecture) how exactly this can be performed in a single clock cycle: P:R1 <- R2, R2 <-R1 where R1 and R2 are registers and P is a control ...
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1answer
37 views

Why don't 2 GPUs double the graphics performance of a computer compared to a single GPU?

Obviously, if you have 2 GPUs, it is double the hardware, and thus it should be double the power of a single GPU (assuming all GPUs are the same, of course). So why is this not the case? I searched ...
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2answers
70 views

Where is Program Counter (PC) stored?

Where is program counter stored? CPU caches? Also how big are these counters? What happens if that memory has been filled up? I know that it's a value that stores the next instruction for the CPU ...
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1answer
103 views

What is memcomputing?

In recent article of PM the memcomputing is presented. But I did not understand how it works, according to the text. What is the general principle of work for this ...
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1answer
58 views

How is the micro code executed within a processor?

How does the microprocessor convert the machine code to micro code? What part of the processor is at play?
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1answer
39 views

pipeline execution time

Lets suppose that 20 percent of the instructions in a program are branch instructions.The static prediction of the jumps supposes that the jumps don't happen. I should find the execution time in two ...
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1answer
31 views

Pipelining and Preemption

According to the concepts of Pipelining, In a single cycle different stages of different instructions are executed. Now I have a bit of confusion here, that if a single processing element is ...
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1answer
28 views

MU0 instruction set

As i know the MU0 processor instruction format is as follows: so the opcode is 4 bit, can anyone explain why it has only 8 instructions, if it could have 16 instructions, 2^4 = 16 ??
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1answer
40 views

RAW Data Hazard resolution

Let's consider the following MIPS (using pipelined arch.) assembly code: lw r1,0(r2) sub r4, r1, r6 and r6, r1, r7 or r8, r1, r9 the r1 value used in the second ...
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1answer
34 views

How does this instruction format limit the number of memory addresses? [closed]

I have come across a question like this. And I don't have any idea how to solve this. Suppose a machine with instruction format of the form opcode A,B,R where ...
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3answers
43 views

Who converts binary/machine code to electrical signals and how?

I went through lots of blogs and posts but could not exactly figure out how the machine code is converted to electrical signals? Any software program is compiled to machine code which is nothing but ...
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2answers
153 views

purpose of supercomputers

Last fall I went on a tour of the Blue Waters supercomputer at the University of Illinois. I asked whether anyone ever used the entire computer. I was told that it was always working on multiple ...
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1answer
44 views

AMAT question cache here [closed]

Suppose that the processor reads cache memory in one clock cycle.In case of cache miss the processor needs 5 clock cycles to read the information in the main memory.What should be the value of Cache ...
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1answer
115 views

How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
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2answers
176 views

Is a 2 address machine more likely to follow a RISC or CISC design?

The Problem: If I have a 3 address machine, is my machine more likely to follow RISC or CISC design? 2 addresses? 1 address? 0 address. To solve this problem I first looked up the different ...
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31 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
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79 views

What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
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1answer
129 views

what are the key advantages of pipelining

I was trying to look my book computer architecture and design, but I can not find the answer for this question. what are-the key-advantages of pipelining?
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91 views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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1answer
25 views

the name of state when data reading from hard drive [closed]

In computer organization and architecture, what is the name of the state when data must be read from hard drive? I have tried to search it on StackOverflow and textbooks but could not find the answer. ...
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2answers
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What happens when the words transfered on the bus are smaller than its width?

So what happens if we're transfering lots of 8 bit words in a 32 bit bus? Does each bus cycle only transfers 8 bit at the time, wasting the other 24 lines of the bus? Or does it transfer 4 words in ...
2
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2answers
148 views

Advantage of byte addressable memory over word addressable memory

What is the reason that almost all computers (besides some DSPs) use byte addressable memory? With byte addressable memory and a 32 bit address you can have 4GB while with word addressable memory you ...
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1answer
43 views

speed, cost and capacity tradoff

I'm reading William Stalling's Operating System Design and internals. Talking about memory, the following tradeoff was introduced: As might be expected, there is a tradeoff among the three key ...
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1answer
36 views

comparison in speed between the processor and the hard disk

I'm reading through William Stalling's operating system intrnals and design principles book. Talking about interrupts, it gives the following examples when comparing the speed of a processor and a ...
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1answer
134 views

Computer Architecture, cache hit and misses

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. One of the ...
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2answers
73 views

Computer Architecture, specifically Amdahl's Law

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. The question I ...
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0answers
77 views

Loading a word from a byte addressed cache

In a cache with byte addressing, the byte you want to load is selected using the block offset. But what if I execute a LW instruction and don't want a single byte but a full 32 bit word? Is there ...
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1answer
134 views

Difference between system bus, address bus and data bus?

What is the difference between system bus, address bus and data bus? Are they different wires or they are using same wires but logically different?
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1answer
39 views

How is a 2-bit predictor better than a 1-bit predictor at determining loop iterations

I have read various explanations why a 1-bit branch predictor is wrong twice per loop, once at the beginning when it wrongly predicts against entering the loop and once at the end when it wrongly ...
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1answer
30 views

Flags register in an out-of-order processor

LW R2, 0(R1) CMP R3, R2 CMP R7, R5 the LW instruction stalls the first CMP so the second one will execute first. Wouldn't this cause the flags register to contain ...
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1answer
42 views

What's the difference between a reorder buffer and an instruction window?

In an out-of-order processor, what is the difference between a reorder buffer and an instruction window? Wikipedia says: "In particular, in a conventional design, the instruction window consists of ...
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What is happening in this part of the LC3? [closed]

This is a diagram of the LC3 Computer I am trying to understand what is happening in the parts I highlighted. The part I had highlighted had the instruction bit sign extended to 16 bits and then ...