A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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References on memory subsystems

I took a typical computer architecture class a long time ago as an undergrad and since then I've done a fair amount of low-level systems programming down to the assembly level and worked on OS ...
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Set Associative Cache - duplicate Tag

In a set associative cache (in this case 4-way) what happens when you try to read an entry with e.g. the tag 0x3B and this tag appears two times within the same set. Given the first is invalid, would ...
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1answer
47 views

Cache question help me here? [closed]

Quantify the effect in performance which comes from using the cache ,if We are going to use a program which is made from 500 machine instructions ,from which 100 are in a cycle which is executed 25 ...
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1answer
44 views

AMAT question cache here [closed]

Suppose that the processor reads cache memory in one clock cycle.In case of cache miss the processor needs 5 clock cycles to read the information in the main memory.What should be the value of Cache ...
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1answer
115 views

How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
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31 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
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79 views

What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
2
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0answers
91 views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
2
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40 views

Understanding pipeline stalls (bubbles) based on stage

I'm currently reading through x86 Assembly Language and C Fundamentals and came across this statement in the second chapter of the book: If the instruction required is not available in the cache, ...
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1answer
35 views

Local Cache miss using MESI Coherence Protocol

My notes on MESI state that there are a few courses of action when we experience a local cache miss on read, depending on the global state of the data (whether other copies already exist, and the ...
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1answer
12 views

Memory Hierarchy and storing data in caches

Question: How many 32 bit integers can be stored in a 16 bit cache line. Answer: 4 can somebody please explain for me why the answer is 4 i did not understand the reason and i think they should give ...
0
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1answer
134 views

Computer Architecture, cache hit and misses

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. One of the ...
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77 views

Loading a word from a byte addressed cache

In a cache with byte addressing, the byte you want to load is selected using the block offset. But what if I execute a LW instruction and don't want a single byte but a full 32 bit word? Is there ...
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1answer
50 views

Can I overcome cache coherence in coding? [closed]

I know that cache coherence is the consistency of shared resource data that ends up stored in multiple local caches. Can any programming languages handle this problem? If so, how?
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39 views

Calculating Effective CPI when using write-through/write-back architecture

So I'm trying to understand a homework problem given by an instructor and I'm honestly lost - I understand the concept of write-through/write-back but, I can't figure out the actual calculations ...
0
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0answers
29 views

Cache Direct-Mapped Index&Tag

I have a question about Direct-Mapped Cache's index and tags. Below is a list of 32-bit memory address references, given as word addresses. 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61 ...
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1answer
64 views

Memory cells (addresses) read into a cache

How does one determine what memory cells (addresses) are being read into a cache? For example if we read at adress "C000EAFCH", which memory cells will be read into the cache if the cache is 64 byte ...
0
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29 views

Cache block offset

When you load data from a cache, you have to specifiy a block offset to select the byte you want. But what do you do if you don't want a single byte but a full 4 byte word?
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1answer
197 views

MIPS rating formula

Could you please help me to understand the mathematics behind MIPS (million instructions per second) rating formula? The formula for MIPS is: $$ \text{MIPS} = \frac{ \text{Instruction ...
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1answer
58 views

Direct Cache Mapping - Addressing

I've looked through all the other similar questions, but I don't feel like I understood exactly what I'm supposed to do with my case, so I'm hoping I'm not the only one. In an exercise I'm doing, I'm ...
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2answers
128 views

Understanding Multilevel Caches

I'm reading multi-level cache and came across a question through which i got confused. I've read that Between processor and Cache Word/ Byte is transfered Between Cache and Main memory ...
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1answer
81 views

How to count bits in cache (direct & 4-way)

Let's say, I have a cache with: 2^32 bytes of memory 2048 blocks (of 16 bytes each) Now I'm trying to figure out how much bits each field will contain. Direct mapped: One block is 16 bytes (16 ...
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1answer
19 views

Why we need tagbits when we already have indexbit and offset?

I was watching a lecture and got confused at one point when professor said that to distinguish between two addresses having same values of offset as well as index bit we need tag.Why we need tag ? for ...
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1answer
93 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
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1answer
83 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
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1answer
122 views

Tag, index and offset of associative cache

My main issue of a homework problem is trying to figure out the different parts of the chart. I have a 3 way set associative cache with 2 word blocks, total size of 24 words. I am given 3, 180, 43, 2, ...
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1answer
2k views

Cache Direct Map (Index, tag, hit/miss)

Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which ...
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1answer
1k views

How to calculate the miss ratio of a cache

I know how to calculate the CPI or cycles per instruction from the hit and miss ratios, but I do not know exactly how to calculate the ...
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1answer
293 views

What problem does cache coloring solve?

According to what I have read from two different sources, cache coloring is (was?) required in order to: Counter the problem of aliasing: Prevent two different virtual addresses with the same ...
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1answer
148 views

Calculating cache memory based on LRU algorithm

Assuming i have 4 blocks of cache memory, Using the LRU (Least Recently Used) replacement algorithm on this following sequence of access to memory blocks: 1 2 3 4 5 2 5 4 1 5 2 3 : ...
2
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58 views

Frigo's cache-oblivious algorithms paper

I am reading Frigo's "Cache-Oblivious Algorithms" paper and I need help understanding his cache complexity expressions for the base cases. He starts on page 3 with "An $s \times s$ submatrix is ...
2
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2answers
125 views

Spatial Locality in Cache - Which addresses are loaded?

I don't quite understand the concept of spatial locality in cacheing. I understand that on a cache miss, not only the specific address we want is loaded into the cache, but also "nearby addresses" are ...
0
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1answer
96 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
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0answers
63 views

L1 and L2 cache

I cannot find a to-the-point reference for my question. Am I correct in assuming that if you have an L1 and an L2 cache, typically the L2 cache linesize is larger? For the following, let's assume a ...
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1answer
66 views

Implementation of caches on CPUs with pipelines

I've read that some current CPUs (e.g. Intel i7 and ARM A9) have (L1) cache latencies of multiple clock cycles while also being pipelined. Some devote multiple pipeline stages to instruction fetching. ...
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What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
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1answer
159 views

Back invalidation to maintain inclusion in inclusive cache

For an L2 cache that is strictly inclusive of the L1 cache, if a block to be evicted is also present in L1, then back invalidation is required to maintain the inclusion property. I am interested in ...
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1answer
728 views

Explanation of Tag, Index, and Offset in Direct Mapping Cache

I'm going through an exercise trying to store address references into a direct mapped cache with 128 blocks and a block size of 32 bytes. The address are 20000, 20004, 20008, and 20016 in base 10. ...
2
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1answer
263 views

How does the OS know the physical address of a process' first memory page?

If I have a program, its instructions are stored on the hard drive. When I double-click the executable the pages of memory for this process must get loaded in to RAM. However, for the pages to get ...
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1answer
911 views

Calculating miss rates of word-addressable and direct-mapped cache

This a problem in a computer architecture course that's giving me some trouble: You have an application whose memory access pattern is a stream and its entire data set is 128kB. The data cache in ...
3
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1answer
502 views

What is the difference between LRU implemented for a cache and for page replacement?

I have read that true LRU page replacement requires significant hardware support, so only approximation of LRU is implemented for page replacement. So I wanted to contrast LRU that is implemented for ...
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90 views

What are current cache algorithms and cache strategies?

Which cache strategies/algorithms (especially for L2 Cache) are used in practice and don't exist solely in research/theory? There is a list on Wikipedia which does not state which algorithms are ...
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216 views

Need help with a set-associative cache memory problem

I'm studying for my Computer Architecture exam next week, and I'm having problems understanding how a set associative cache works and how to solve related problems like this one : "A set-associative ...
4
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1answer
106 views

Are cache contents specific to a process? [duplicate]

Suppose the L1 cache is filled up with data from some process. Now CPU loads another process. Does the new process share cache contents? Or the cache has to be invalidated completely in each context ...
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1answer
33 views

Effective computation on linear data without random access

recently I've started thinking about caching problems in modern CPUs, where they struggle to adequately fetch program data (not instructions) in time, so that it can be computed further. So then I ...
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1answer
29 views

Difference in CPU Wattage Question [closed]

If I have 2 CPU's of the same manufacturer... say AMD Both are Quad-Core, Both are rated at 3.6Ghz 1 is 100W, the other is 65W Will the one with the higher wattage out-perform the lower one and ...
2
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3answers
122 views

Does exploiting a spatial Locality in Cache always leads to a lower miss rate?

I've read that, incorporating many words(spatial locality) per cache blocks leads to lower miss rate. Is it the case always? One possibility of such approach is to make a single cache block of size ...
3
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0answers
30 views

How do you compare algorithms based on scaling of their cache misses? [duplicate]

We all know how to use “Big O” notation to show how CPU instructions run increase as the size of the dataset increases. E.g. a quick sort is O(n log n). However for the last few years, ...
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1answer
421 views

CPU bit, its cache line, the bus between memory and CPU, and its registers?

Should the size of its cache line, the width of bus between memory and CPU, and the size of its registers be all equal to the CPU bit? Is CPU bit determined by the size of its cache line, the width ...
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1answer
50 views

Why we need to read memory on a write-miss?

I noticed that in write-back cache memories, when cpu want to write on a block, it should fetch it from memory then update that block. so if block is going to be overwritten and changed by processor, ...