A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Why we need tagbits when we already have indexbit and offset?

I was watching a lecture and got confused at one point when professor said that to distinguish between two addresses having same values of offset as well as index bit we need tag.Why we need tag ? for ...
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42 views

Direct Mapped Cache: Number of blocks replaced

I am working on this problem: Starting from power on, the following byte-addressed cache references are recorded. ...
-1
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1answer
15 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
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19 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
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0answers
31 views

Tag, index and offset of associative cache

My main issue of a homework problem is trying to figure out the different parts of the chart. I have a 3 way set associative cache with 2 word blocks, total size of 24 words. I am given 3, 180, 43, 2, ...
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1answer
104 views

Cache Direct Map (Index, tag, hit/miss)

Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which ...
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1answer
40 views

How to calculate the miss ratio of a cache

I know how to calculate the CPI or cycles per instruction from the hit and miss ratios, but I do not know exactly how to calculate the ...
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1answer
62 views

What problem does cache coloring solve?

According to what I have read from two different sources, cache coloring is (was?) required in order to: Counter the problem of aliasing: Prevent two different virtual addresses with the same ...
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1answer
60 views

Calculating cache memory based on LRU algorithm

Assuming i have 4 blocks of cache memory, Using the LRU (Least Recently Used) replacement algorithm on this following sequence of access to memory blocks: 1 2 3 4 5 2 5 4 1 5 2 3 : ...
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0answers
41 views

Frigo's cache-oblivious algorithms paper

I am reading Frigo's "Cache-Oblivious Algorithms" paper and I need help understanding his cache complexity expressions for the base cases. He starts on page 3 with "An $s \times s$ submatrix is ...
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2answers
93 views

Spatial Locality in Cache - Which addresses are loaded?

I don't quite understand the concept of spatial locality in cacheing. I understand that on a cache miss, not only the specific address we want is loaded into the cache, but also "nearby addresses" are ...
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1answer
62 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
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47 views

L1 and L2 cache

I cannot find a to-the-point reference for my question. Am I correct in assuming that if you have an L1 and an L2 cache, typically the L2 cache linesize is larger? For the following, let's assume a ...
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1answer
45 views

Implementation of caches on CPUs with pipelines

I've read that some current CPUs (e.g. Intel i7 and ARM A9) have (L1) cache latencies of multiple clock cycles while also being pipelined. Some devote multiple pipeline stages to instruction fetching. ...
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3answers
1k views

What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
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1answer
50 views

Back invalidation to maintain inclusion in inclusive cache

For an L2 cache that is strictly inclusive of the L1 cache, if a block to be evicted is also present in L1, then back invalidation is required to maintain the inclusion property. I am interested in ...
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1answer
196 views

Explanation of Tag, Index, and Offset in Direct Mapping Cache

I'm going through an exercise trying to store address references into a direct mapped cache with 128 blocks and a block size of 32 bytes. The address are 20000, 20004, 20008, and 20016 in base 10. ...
2
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1answer
114 views

How does the OS know the physical address of a process' first memory page?

If I have a program, its instructions are stored on the hard drive. When I double-click the executable the pages of memory for this process must get loaded in to RAM. However, for the pages to get ...
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1answer
219 views

Calculating miss rates of word-addressable and direct-mapped cache

This a problem in a computer architecture course that's giving me some trouble: You have an application whose memory access pattern is a stream and its entire data set is 128kB. The data cache in ...
3
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1answer
173 views

What is the difference between LRU implemented for a cache and for page replacement?

I have read that true LRU page replacement requires significant hardware support, so only approximation of LRU is implemented for page replacement. So I wanted to contrast LRU that is implemented for ...
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0answers
62 views

What are current cache algorithms and cache strategies?

Which cache strategies/algorithms (especially for L2 Cache) are used in practice and don't exist solely in research/theory? There is a list on Wikipedia which does not state which algorithms are ...
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0answers
149 views

Need help with a set-associative cache memory problem

I'm studying for my Computer Architecture exam next week, and I'm having problems understanding how a set associative cache works and how to solve related problems like this one : "A set-associative ...
3
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1answer
79 views

Are cache contents specific to a process?

Suppose the L1 cache is filled up with data from some process. Now CPU loads another process. Does the new process share cache contents? Or the cache has to be invalidated completely in each context ...
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1answer
30 views

Effective computation on linear data without random access

recently I've started thinking about caching problems in modern CPUs, where they struggle to adequately fetch program data (not instructions) in time, so that it can be computed further. So then I ...
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1answer
25 views

Difference in CPU Wattage Question [closed]

If I have 2 CPU's of the same manufacturer... say AMD Both are Quad-Core, Both are rated at 3.6Ghz 1 is 100W, the other is 65W Will the one with the higher wattage out-perform the lower one and ...
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3answers
66 views

Does exploiting a spatial Locality in Cache always leads to a lower miss rate?

I've read that, incorporating many words(spatial locality) per cache blocks leads to lower miss rate. Is it the case always? One possibility of such approach is to make a single cache block of size ...
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30 views

How do you compare algorithms based on scaling of their cache misses? [duplicate]

We all know how to use “Big O” notation to show how CPU instructions run increase as the size of the dataset increases. E.g. a quick sort is O(n log n). However for the last few years, ...
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1answer
225 views

CPU bit, its cache line, the bus between memory and CPU, and its registers?

Should the size of its cache line, the width of bus between memory and CPU, and the size of its registers be all equal to the CPU bit? Is CPU bit determined by the size of its cache line, the width ...
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1answer
33 views

Why we need to read memory on a write-miss?

I noticed that in write-back cache memories, when cpu want to write on a block, it should fetch it from memory then update that block. so if block is going to be overwritten and changed by processor, ...
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696 views

Memory Consistency vs Cache Coherence

Could you please check (and probably clarify) my understanding of the difference between these two concepts: Sequential Consistency and Cache Coherence? According to this paper[1] sequential ...
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38 views

Finding TLB hit and miss [duplicate]

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nsec and servicing a page fault takes 8 millisec. An average instruction takes 100 nsec of CPU time and two ...
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1answer
69 views

Owned state in MOESI protocol-transitions?

I understand that MESI is a subset of the MOESI cache coherency protocol. But what does the Owned state in the MOESI protocol represent? What are the differences in state transition due to the extra ...
2
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1answer
102 views

MESI Protocol Invalid cache line is attempted to be stored?

I am implementing a sample MESI simulator having two levels of cache (write back). I have added MESI status bits to both levels of cache. As it is a write back cache, the cache line is updated to L2 ...
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394 views

Parallelising random reads seems to work well — why?

Consider the following very simple computer program: for i = 1 to n: y[i] = x[p[i]] Here $x$ and $y$ are $n$-element arrays of bytes, and $p$ is an ...
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550 views

What determines a hit/miss with cache memory?

I was taught that when a reference is mapped to a cache block, X, for the first time, the word is stored in the cache block, bearing a tag and index that helps identify it for future reads. Then, ...
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1answer
97 views

In cache addressing, what value is placed in the offset field?

There is a 64 KB 1-word cache, and a word is 32 bits. From that I can derive that the length of the tag field is 16 bits, the length of index field is 14 bits, and, as my professor taught me, there ...
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2answers
80 views

In cache-oblivious algorithms, how is recursive reduction of data performed?

From wikipedia: "Typically, a cache-oblivious algorithm works by a recursive divide and conquer algorithm, where the problem is divided into smaller and smaller subproblems. Eventually, one reaches a ...
2
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1answer
1k views

How does a TLB and data cache work?

I'm trying to study for an exam and I realized I'm confused about how the TLB and data cache work. I understand that the TLB is essentially a cache of most recently used physical addresses. However, ...
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2answers
152 views

How to avoid column wise access in matrix multiplication?

I know when we access elements in rows it will be much faster than if it is accessed column wise. In matrix multiplication one of the matrices must be accessed column wise. In GPUs with CUDA/OpenCL ...
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1answer
957 views

Understanding the basic concepts in memory organisation

(Before actually proceeding to the question, I want to confess that this is a homework question, please do consider it and help me in improving my understanding a bit more.) I have recently started ...
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137 views

Is there a prefered name for the “effective access time” formula?

Any CS class about caches will at some point address this classical formula (or a variant of it) Effective_access_time = hit_time + miss_penalty * miss_rate My ...
4
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1answer
484 views

Performance of row- vs. column-wise matrix traversal

Scott Meyers describes here that traversing a symmetric matrix row-wise performes significantly better over traversing it column-wise - which is also significantly counter-intuitive. The reasoning ...
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1answer
358 views

Multi-level cache for which inclusion holds [closed]

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary? L1 must be a write-through cache. L2 must be a write-through cache. ...
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3answers
16k views

How to calculate the tag, index and offset fields of different caches?

Specifically: 1) A direct-mapped cache with 4096 blocks/lines in which each block has 8 32-bit words. How many bits are needed for the tag and index fields, assuming a 32-bit address? 2) Same ...
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1answer
100 views

In the “tall cache assumption” what does $\Omega$ represent?

Within the field of cache-oblivious algorithms the ideal cache model is used for determining the cache complexity of an algorithm. One of the assumptions of the ideal cache model is that it models a ...
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0answers
89 views

How many words loaded on a cache miss

Regarding Processor Direct Cache, what is the proper mathematical technique for discovering how many words are loaded on a cache miss? For example if you have a direct mapped cache with a total data ...
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3answers
718 views

Finding cache block transfer time in a 3 level memory system

Following question was asked in one of entrance exams for a graduation programme. Please help me try to solve it : A computer system has an L1 cache, an L2 cache, and a main memory unity ...
2
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2answers
538 views

Finding hit ratio of a cache

Consider an array A[100] & each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. Assume one block is read into ...
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3answers
183 views

CPU Cache is managed by which software component?

CPU caches are used by exploiting temporal and spatial locality. My question is who is responsible for managing these caches? Is this Operating system that identifies a particular access pattern and ...
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3answers
221 views

Does the write through cache copies the whole block or just the byte which is updated?

Just a basic question to ask Does the write through cache copies the whole block or just the byte which is updated? I went through the following question Array A contains 256 elements of 4 bytes ...