A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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TAG dimension in Direct Mapping and N-way associative

someone can help with this quiz: 1) We have a direct mapping cache memory with 2^10 lines. Each line is hosting 32 data. How many bits are necessary for the TAG for a 24 bits address bus? 2) We ...
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41 views

How do stack-based cache algorithms avoid Belady's anomaly?

I was going through page replacement algorithms from Galvin's Operating System book. I encountered this line about LRU: A stack algorithm is one in which the pages kept in memory for a frame set ...
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2answers
50 views

Pros and Cons of Average Memory Access Time When Increasing Cache Block Size

Assuming we have a single-level (L1) cache and main memory, what are some of the advantages and disadvantages of having a larger cache block size (considering average memory access time). The only ...
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2answers
28 views

Increasing Cache Line and Programs with bad Spatial Locality

I'm reading on caches and I'm feeling a bit lost with spatial locality. From my understanding, increasing the cache line with a program that has high spatial locality reduces the miss rate. But for ...
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18 views

Miss penalty for Write request in a Write-Back style system

If the processor is trying to write a word to a certain memory location, and the system uses a write-back style architecture, what happens in case of a miss? I'm assuming that the system would first ...
2
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22 views

Is it possible to figure out cache size and associativity using the length of offset, index, tag fields?

I have a question where I am asked to find the size of a cache. I am given the following info: a) the length of a memory address b) the number of bits for offset, index, and tag fields. I know I ...
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1answer
104 views

Computing the hit and miss ratio of a cache organized as either direct mapped or two-way associative

This is an example problem in a computer organization and architecture course that's giving me some trouble. It goes as follows: Consider a cache of 4 lines of 16 bytes each. Main memory is ...
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29 views

Hashtable vs cache-oblivious

This question has been asked in the theoretical community, but deemed as too practical. I am moving it here, I hope it is on-topic. I'd like to know more about real performances of data structures, ...
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1answer
31 views

How is parallel tag checking achieved in associative Mapping?

I originally posted this question on stack overflow and then realised it was better suited to computer science . In the book on computer organization and architecture by William stallings , in the ...
5
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1answer
113 views

Why is quiescent consistency compositional, but sequential consistency is not

I'm having trouble in comparing these two memory consistency models. Essentially for sequential consistency I think of real code like this: ...
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64 views

Difference between capacity miss and conflict miss

Premise: Two types of cache miss: capacity miss, conflict miss\ Cache contains only 2 sets, SET 1 and SET 2 Problem: If data A maps to SET 1 and it doesn't exist in SET 1 while SET 1 is fully ...
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37 views

Performance on modifying cycle time

I learnt in my computer architecture course on Caches, that if we keep the memory speed of a machine the same and half the clock cycle time, the miss penalty doubles. Why does this happen? What is ...
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2answers
55 views

What's the difference between clock replacement & LRU replacement?

As title. When we want to request following page numbers 2,4,4,2,5,2,1,1,3,1, is clock replacement better? What are the advantages and disadvantages of them? Thanks~
6
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1answer
87 views

How to compute $\mathbf{X}^T \mathbf{X}$ efficiently for large $\mathbf{X}$?

Let $\mathbf{X}$ be a $n \times n$ matrix. Given that we can only keep $k$ rows ($k << n$) or columns of the matrix in memory, how can we compute $\mathbf{X}^T \mathbf{X}$ while minimizing the ...
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0answers
27 views

Average Time for Write Through & Write Back policies

Tc -> cache updation time(per word) Tm -> main memory updation time(per word) Tb -> updation time of a block (Both policies below don't follow a strict hierarchy. i.e. if there is a miss the ...
3
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2answers
105 views

Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
3
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1answer
25 views

Why do caches fetch data to the right if the offset bit is 0 and to the left if it is 1 in a 2-word block

Here is an example of table with 32 bit addresses and their respective indexes and tags. The cache has a total of 8 blocks and 2-word blocks. So since we have 2 word blocks, that means that the ...
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2answers
52 views

Computer cache - data removing

I am programming CPU cache simulator and I am supposed to implement removing of entries. I will not use LRU but just random. I am not really clear, when should I call the removing function? When ...
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1answer
17 views

Know when we have a cache default and if it loads

I have an exercise about cache memory, first the cache is empty : I have a cache memory with 16 lines and each lines have 16 octet, the address is 16 bits So I know that the INDEX will be composed of ...
3
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1answer
42 views

Direct mapping cache with LRU

I'm studying computer architecture and I'm doing an experiment. Does LRU make sense in a direct mapping cache? I'm quite confused. Thank you.
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3answers
101 views

Depth first or breadth first ordering in binary search trees?

Let's say that I make a binary search tree and store it in an array so that I end up with an array that is more cache friendly to binary search compared to a sorted array. The binary tree is full on ...
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2answers
61 views

Does having one large L1 cache instead of L1 and L2 cache makes computation faster?

Does having one larger L1 cache instead of L1 and L2 cache makes computation faster? Also will this make the CPU more expensive to make?
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2answers
110 views

In a $k$-way set associative cache,main memory block mapping in range?

In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are ...
2
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2answers
42 views

Caches and reading a PDF

I am currently learning about caches in Systems class, and I had a few doubts about what exactly happens when a Computer reads a PDF. This is the sequence that happens in my mind: The CPU checks if ...
2
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1answer
179 views

How can i compute tag-index-displacement bits of an address if cache size is not a power of two?

How can i compute tag-index-displacement bits from an address if cache size is not a power of two? Intuitively, i would be inclined to think that i can not directly indicate which bits of the address ...
2
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1answer
151 views

What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...
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2answers
90 views

Question about set-associative cache mapping

I found a question: Let a two-way set-associative cache of 4 memory blocks, each block containing one word. What is the number of misses and hits considering the following sequence of block ...
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338 views

Solving for Hit Ratio of a Theoretical Memory System

Long time lurker, first time poster. The book I am reading is William Stalling's "Operating Systems: Internals and Design Principles" Seventh Edition. Stalling's definition of hit ratio according to ...
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159 views

How do you calculate when effective access time is greater than cache access time?

I'm having trouble understanding how to calculate effective access time, hit ratios and cache access times. I'm unfamiliar with the concepts and would love help, or an explanation on how to solve this ...
3
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0answers
38 views

References on memory subsystems

I took a typical computer architecture class a long time ago as an undergrad and since then I've done a fair amount of low-level systems programming down to the assembly level and worked on OS kernels....
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2answers
55 views

Set Associative Cache - duplicate Tag

In a set associative cache (in this case 4-way) what happens when you try to read an entry with e.g. the tag 0x3B and this tag appears two times within the same set. Given the first is invalid, would ...
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1answer
53 views

Cache question help me here? [closed]

Quantify the effect in performance which comes from using the cache ,if We are going to use a program which is made from 500 machine instructions ,from which 100 are in a cycle which is executed 25 ...
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1answer
588 views

AMAT question cache here [closed]

Suppose that the processor reads cache memory in one clock cycle.In case of cache miss the processor needs 5 clock cycles to read the information in the main memory.What should be the value of Cache ...
0
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1answer
411 views

How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
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34 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
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0answers
159 views

What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
2
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0answers
351 views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
4
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1answer
153 views

Understanding pipeline stalls (bubbles) based on stage

I'm currently reading through x86 Assembly Language and C Fundamentals and came across this statement in the second chapter of the book: If the instruction required is not available in the cache, ...
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1answer
82 views

Local Cache miss using MESI Coherence Protocol

My notes on MESI state that there are a few courses of action when we experience a local cache miss on read, depending on the global state of the data (whether other copies already exist, and the ...
0
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1answer
14 views

Memory Hierarchy and storing data in caches

Question: How many 32 bit integers can be stored in a 16 bit cache line. Answer: 4 can somebody please explain for me why the answer is 4 i did not understand the reason and i think they should give ...
0
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1answer
647 views

Computer Architecture, cache hit and misses

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. One of the ...
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1answer
104 views

Loading a word from a byte addressed cache

In a cache with byte addressing, the byte you want to load is selected using the block offset. But what if I execute a LW instruction and don't want a single byte but a full 32 bit word? Is there ...
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1answer
78 views

Can I overcome cache coherence in coding? [closed]

I know that cache coherence is the consistency of shared resource data that ends up stored in multiple local caches. Can any programming languages handle this problem? If so, how?
0
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1answer
103 views

Memory cells (addresses) read into a cache

How does one determine what memory cells (addresses) are being read into a cache? For example if we read at adress "C000EAFCH", which memory cells will be read into the cache if the cache is 64 byte ...
0
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1answer
2k views

MIPS rating formula

Could you please help me to understand the mathematics behind MIPS (million instructions per second) rating formula? The formula for MIPS is: $$ \text{MIPS} = \frac{ \text{Instruction count}}{\...
0
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1answer
141 views

Direct Cache Mapping - Addressing

I've looked through all the other similar questions, but I don't feel like I understood exactly what I'm supposed to do with my case, so I'm hoping I'm not the only one. In an exercise I'm doing, I'm ...
0
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2answers
369 views

Understanding Multilevel Caches

I'm reading multi-level cache and came across a question through which i got confused. I've read that Between processor and Cache Word/ Byte is transfered Between Cache and Main memory Block(...
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1answer
154 views

How to count bits in cache (direct & 4-way)

Let's say, I have a cache with: 2^32 bytes of memory 2048 blocks (of 16 bytes each) Now I'm trying to figure out how much bits each field will contain. Direct mapped: One block is 16 bytes (16 ...
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1answer
19 views

Why we need tagbits when we already have indexbit and offset?

I was watching a lecture and got confused at one point when professor said that to distinguish between two addresses having same values of offset as well as index bit we need tag.Why we need tag ? for ...
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1answer
229 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...