A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Average Time for Write Through & Write Back policies

Tc -> cache updation time(per word) Tm -> main memory updation time(per word) Tb -> updation time of a block (Both policies below don't follow a strict hierarchy. i.e. if there is a miss the ...
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89 views

Identifying system events affecting timing behavior of an application

Q: What are those events (system level and architecture level) that can cause an application to take longer to terminate and complete the job? My question is purely in the context of Worst Case ...
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18 views

Why do caches fetch data to the right if the offset bit is 0 and to the left if it is 1 in a 2-word block

Here is an example of table with 32 bit addresses and their respective indexes and tags. The cache has a total of 8 blocks and 2-word blocks. So since we have 2 word blocks, that means that the ...
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48 views

Computer cache - data removing

I am programming CPU cache simulator and I am supposed to implement removing of entries. I will not use LRU but just random. I am not really clear, when should I call the removing function? When ...
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1answer
17 views

Know when we have a cache default and if it loads

I have an exercise about cache memory, first the cache is empty : I have a cache memory with 16 lines and each lines have 16 octet, the address is 16 bits So I know that the INDEX will be composed of ...
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34 views

Direct mapping cache with LRU

I'm studying computer architecture and I'm doing an experiment. Does LRU make sense in a direct mapping cache? I'm quite confused. Thank you.
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58 views

Depth first or breadth first ordering in binary search trees?

Let's say that I make a binary search tree and store it in an array so that I end up with an array that is more cache friendly to binary search compared to a sorted array. The binary tree is full on ...
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2answers
44 views

Does having one large L1 cache instead of L1 and L2 cache makes computation faster?

Does having one larger L1 cache instead of L1 and L2 cache makes computation faster? Also will this make the CPU more expensive to make?
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71 views

In a $k$-way set associative cache,main memory block mapping in range?

In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are ...
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40 views

Caches and reading a PDF

I am currently learning about caches in Systems class, and I had a few doubts about what exactly happens when a Computer reads a PDF. This is the sequence that happens in my mind: The CPU checks if ...
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1answer
109 views

How can i compute tag-index-displacement bits of an address if cache size is not a power of two?

How can i compute tag-index-displacement bits from an address if cache size is not a power of two? Intuitively, i would be inclined to think that i can not directly indicate which bits of the address ...
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1answer
119 views

What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...
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53 views

Question about set-associative cache mapping

I found a question: Let a two-way set-associative cache of 4 memory blocks, each block containing one word. What is the number of misses and hits considering the following sequence of block ...
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145 views

Solving for Hit Ratio of a Theoretical Memory System

Long time lurker, first time poster. The book I am reading is William Stalling's "Operating Systems: Internals and Design Principles" Seventh Edition. Stalling's definition of hit ratio according to ...
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134 views

How do you calculate when effective access time is greater than cache access time?

I'm having trouble understanding how to calculate effective access time, hit ratios and cache access times. I'm unfamiliar with the concepts and would love help, or an explanation on how to solve this ...
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36 views

References on memory subsystems

I took a typical computer architecture class a long time ago as an undergrad and since then I've done a fair amount of low-level systems programming down to the assembly level and worked on OS ...
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36 views

Set Associative Cache - duplicate Tag

In a set associative cache (in this case 4-way) what happens when you try to read an entry with e.g. the tag 0x3B and this tag appears two times within the same set. Given the first is invalid, would ...
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1answer
52 views

Cache question help me here? [closed]

Quantify the effect in performance which comes from using the cache ,if We are going to use a program which is made from 500 machine instructions ,from which 100 are in a cycle which is executed 25 ...
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1answer
286 views

AMAT question cache here [closed]

Suppose that the processor reads cache memory in one clock cycle.In case of cache miss the processor needs 5 clock cycles to read the information in the main memory.What should be the value of Cache ...
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1answer
313 views

How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
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32 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
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136 views

What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
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256 views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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91 views

Understanding pipeline stalls (bubbles) based on stage

I'm currently reading through x86 Assembly Language and C Fundamentals and came across this statement in the second chapter of the book: If the instruction required is not available in the cache, ...
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1answer
61 views

Local Cache miss using MESI Coherence Protocol

My notes on MESI state that there are a few courses of action when we experience a local cache miss on read, depending on the global state of the data (whether other copies already exist, and the ...
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1answer
13 views

Memory Hierarchy and storing data in caches

Question: How many 32 bit integers can be stored in a 16 bit cache line. Answer: 4 can somebody please explain for me why the answer is 4 i did not understand the reason and i think they should give ...
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356 views

Computer Architecture, cache hit and misses

I am currently enrolled in a computer organization and design class, which I am struggling mightily with, and I have a final homework in my class that I need to get a perfect score on. One of the ...
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88 views

Loading a word from a byte addressed cache

In a cache with byte addressing, the byte you want to load is selected using the block offset. But what if I execute a LW instruction and don't want a single byte but a full 32 bit word? Is there ...
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1answer
71 views

Can I overcome cache coherence in coding? [closed]

I know that cache coherence is the consistency of shared resource data that ends up stored in multiple local caches. Can any programming languages handle this problem? If so, how?
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70 views

Calculating Effective CPI when using write-through/write-back architecture

So I'm trying to understand a homework problem given by an instructor and I'm honestly lost - I understand the concept of write-through/write-back but, I can't figure out the actual calculations ...
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46 views

Cache Direct-Mapped Index&Tag

I have a question about Direct-Mapped Cache's index and tags. Below is a list of 32-bit memory address references, given as word addresses. 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61 ...
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80 views

Memory cells (addresses) read into a cache

How does one determine what memory cells (addresses) are being read into a cache? For example if we read at adress "C000EAFCH", which memory cells will be read into the cache if the cache is 64 byte ...
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47 views

Cache block offset

When you load data from a cache, you have to specifiy a block offset to select the byte you want. But what do you do if you don't want a single byte but a full 4 byte word?
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1answer
1k views

MIPS rating formula

Could you please help me to understand the mathematics behind MIPS (million instructions per second) rating formula? The formula for MIPS is: $$ \text{MIPS} = \frac{ \text{Instruction ...
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93 views

Direct Cache Mapping - Addressing

I've looked through all the other similar questions, but I don't feel like I understood exactly what I'm supposed to do with my case, so I'm hoping I'm not the only one. In an exercise I'm doing, I'm ...
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293 views

Understanding Multilevel Caches

I'm reading multi-level cache and came across a question through which i got confused. I've read that Between processor and Cache Word/ Byte is transfered Between Cache and Main memory ...
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1answer
117 views

How to count bits in cache (direct & 4-way)

Let's say, I have a cache with: 2^32 bytes of memory 2048 blocks (of 16 bytes each) Now I'm trying to figure out how much bits each field will contain. Direct mapped: One block is 16 bytes (16 ...
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1answer
19 views

Why we need tagbits when we already have indexbit and offset?

I was watching a lecture and got confused at one point when professor said that to distinguish between two addresses having same values of offset as well as index bit we need tag.Why we need tag ? for ...
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1answer
151 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
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124 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
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1answer
226 views

Tag, index and offset of associative cache

My main issue of a homework problem is trying to figure out the different parts of the chart. I have a 3 way set associative cache with 2 word blocks, total size of 24 words. I am given 3, 180, 43, 2, ...
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1answer
5k views

Cache Direct Map (Index, tag, hit/miss)

Alright, I thought I understood this concept but now I am confused. I looked up similar problems and their solutions to practice, and that's what threw me off. The question is a homework problem which ...
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1answer
4k views

How to calculate the miss ratio of a cache

I know how to calculate the CPI or cycles per instruction from the hit and miss ratios, but I do not know exactly how to calculate the ...
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1answer
548 views

What problem does cache coloring solve?

According to what I have read from two different sources, cache coloring is (was?) required in order to: Counter the problem of aliasing: Prevent two different virtual addresses with the same ...
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1answer
213 views

Calculating cache memory based on LRU algorithm

Assuming i have 4 blocks of cache memory, Using the LRU (Least Recently Used) replacement algorithm on this following sequence of access to memory blocks: 1 2 3 4 5 2 5 4 1 5 2 3 : ...
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66 views

Frigo's cache-oblivious algorithms paper

I am reading Frigo's "Cache-Oblivious Algorithms" paper and I need help understanding his cache complexity expressions for the base cases. He starts on page 3 with "An $s \times s$ submatrix is ...
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2answers
132 views

Spatial Locality in Cache - Which addresses are loaded?

I don't quite understand the concept of spatial locality in cacheing. I understand that on a cache miss, not only the specific address we want is loaded into the cache, but also "nearby addresses" are ...
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2answers
158 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
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67 views

L1 and L2 cache

I cannot find a to-the-point reference for my question. Am I correct in assuming that if you have an L1 and an L2 cache, typically the L2 cache linesize is larger? For the following, let's assume a ...
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75 views

Implementation of caches on CPUs with pipelines

I've read that some current CPUs (e.g. Intel i7 and ARM A9) have (L1) cache latencies of multiple clock cycles while also being pipelined. Some devote multiple pipeline stages to instruction fetching. ...