A fast memory limited in space close to the CPU. A cache is designed to reduce the average time to access memory.

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Difference in CPU Wattage Question

If I have 2 CPU's of the same manufacturer... say AMD Both are Quad-Core, Both are rated at 3.6Ghz 1 is 100W, the other is 65W Will the one with the higher wattage out-perform the lower one and ...
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Caches: connection between a given code and a cache

I have completed a computer architecture course and the last topic i have learned was cache memories. I have peeked in random tests of course from the last few years and all of them have a given mips ...
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Does exploiting a spatial Locality in Cache always leads to a lower miss rate?

I've read that, incorporating many words(spatial locality) per cache blocks leads to lower miss rate. Is it the case always? One possibility of such approach is to make a single cache block of size ...
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How do you compare algorithms based on scaling of their cache misses?

We all know how to use “Big O” notation to show how CPU instructions run increase as the size of the dataset increases. E.g. a quick sort is O(n log n). However for the last few years, ...
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CPU bit, its cache line, the bus between memory and CPU, and its registers?

Should the size of its cache line, the width of bus between memory and CPU, and the size of its registers be all equal to the CPU bit? Is CPU bit determined by the size of its cache line, the width ...
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Why we need to read memory on a write-miss?

I noticed that in write-back cache memories, when cpu want to write on a block, it should fetch it from memory then update that block. so if block is going to be overwritten and changed by processor, ...
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Memory Consistency vs Cache Coherence

Could you please check (and probably clarify) my understanding of the difference between these two concepts: Sequential Consistency and Cache Coherence? According to this paper[1] sequential ...
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38 views

Finding TLB hit and miss [duplicate]

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nsec and servicing a page fault takes 8 millisec. An average instruction takes 100 nsec of CPU time and two ...
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33 views

Owned state in MOESI protocol-transitions?

I understand that MESI is a subset of the MOESI cache coherency protocol. But what does the Owned state in the MOESI protocol represent? What are the differences in state transition due to the extra ...
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MESI Protocol Invalid cache line is attempted to be stored?

I am implementing a sample MESI simulator having two levels of cache (write back). I have added MESI status bits to both levels of cache. As it is a write back cache, the cache line is updated to L2 ...
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357 views

Parallelising random reads seems to work well — why?

Consider the following very simple computer program: for i = 1 to n: y[i] = x[p[i]] Here $x$ and $y$ are $n$-element arrays of bytes, and $p$ is an ...
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What determines a hit/miss with cache memory?

I was taught that when a reference is mapped to a cache block, X, for the first time, the word is stored in the cache block, bearing a tag and index that helps identify it for future reads. Then, ...
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In cache addressing, what value is placed in the offset field?

There is a 64 KB 1-word cache, and a word is 32 bits. From that I can derive that the length of the tag field is 16 bits, the length of index field is 14 bits, and, as my professor taught me, there ...
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In cache-oblivious algorithms, how is recursive reduction of data performed?

From wikipedia: "Typically, a cache-oblivious algorithm works by a recursive divide and conquer algorithm, where the problem is divided into smaller and smaller subproblems. Eventually, one reaches a ...
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179 views

How does a TLB and data cache work?

I'm trying to study for an exam and I realized I'm confused about how the TLB and data cache work. I understand that the TLB is essentially a cache of most recently used physical addresses. However, ...
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How to avoid column wise access in matrix multiplication?

I know when we access elements in rows it will be much faster than if it is accessed column wise. In matrix multiplication one of the matrices must be accessed column wise. In GPUs with CUDA/OpenCL ...
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Understanding the basic concepts in memory organisation

(Before actually proceeding to the question, I want to confess that this is a homework question, please do consider it and help me in improving my understanding a bit more.) I have recently started ...
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Is there a prefered name for the “effective access time” formula?

Any CS class about caches will at some point address this classical formula (or a variant of it) Effective_access_time = hit_time + miss_penalty * miss_rate My ...
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Average Memory Access Time for Split/2-Level Cache

I am trying to calculate the average memory access time of a 2-level cache with a split L1 cache. I am given the 3 formulas below: Given Basic Formula: ...
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Performance of row- vs. column-wise matrix traversal

Scott Meyers describes here that traversing a symmetric matrix row-wise performes significantly better over traversing it column-wise - which is also significantly counter-intuitive. The reasoning ...
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191 views

Multi-level cache for which inclusion holds [closed]

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary? L1 must be a write-through cache. L2 must be a write-through cache. ...
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How to calculate the tag, index and offset fields of different caches?

Specifically: 1) A direct-mapped cache with 4096 blocks/lines in which each block has 8 32-bit words. How many bits are needed for the tag and index fields, assuming a 32-bit address? 2) Same ...
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In the “tall cache assumption” what does $\Omega$ represent?

Within the field of cache-oblivious algorithms the ideal cache model is used for determining the cache complexity of an algorithm. One of the assumptions of the ideal cache model is that it models a ...
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How many words loaded on a cache miss

Regarding Processor Direct Cache, what is the proper mathematical technique for discovering how many words are loaded on a cache miss? For example if you have a direct mapped cache with a total data ...
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Finding cache block transfer time in a 3 level memory system

Following question was asked in one of entrance exams for a graduation programme. Please help me try to solve it : A computer system has an L1 cache, an L2 cache, and a main memory unity ...
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Finding hit ratio of a cache

Consider an array A[100] & each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. Assume one block is read into ...
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CPU Cache is managed by which software component?

CPU caches are used by exploiting temporal and spatial locality. My question is who is responsible for managing these caches? Is this Operating system that identifies a particular access pattern and ...
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Does the write through cache copies the whole block or just the byte which is updated?

Just a basic question to ask Does the write through cache copies the whole block or just the byte which is updated? I went through the following question Array A contains 256 elements of 4 bytes ...
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Cache strategies, what reference article could I study?

So as to optimize an application, I must implement data caching: not to recompute some data - those heavy on cpu but that don't change often. When playing with the idea, I imagined something like the ...
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Doubt regarding cache hit ratios and access time

Question 1: What is the average access time for a 3-level memory system with access time $T_1$, $2T_1$ and $3T_1$? (Hit ratio $h_1$ = $h_2$ = 0.9) The solution given is: $0.9[T_1] + 0.1(0.9[2*T_1] + ...
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Determine interference factors in parallel computing

Parallel processes interfere with each other in many ways, by competing for shared resources such as shared caches, memory, disks, etc. Would it be possible to determine latent factors just with a ...
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Why can L3 caches hold only shared blocks?

In a recent CACM article [1], the authors present a way to improve scalability of shared and coherent caches. The core ingredient is assuming the caches are inclusive, that is higher-level caches ...
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What happens to the cache contents on a context switch?

In a multicore processor, what happens to the contents of a core's cache (say L1) when a context switch occurs on that cache? Is the behaviour dependent on the architecture or is it a general ...
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Research on evaluating the performance of cache-obliviousness in practice

Cache-oblivious algorithms and data structures are a rather new thing, introduced by Frigo et al. in Cache-oblivious algorithms, 1999. Prokop's thesis from the same year introduces the early ideas as ...
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Are generational garbage collectors inherently cache-friendly?

A typical generational garbage collector keeps recently allocated data in a separate memory region. In typical programs, a lot of data is short-lived, so collecting young garbage (a minor GC cycle) ...