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12
votes
3answers
1k views

What does the processor do while waiting for a main memory fetch

Assuming l1 and l2 cache requests result in a miss, does the processor stall until main memory has been accessed? I heard about the idea of switching to another thread, if so what is used to wake up ...
0
votes
2answers
20 views

Calculating speedup for a two-way superscalar cpu

I've been coming across a problem in one of my assignments requiring the calculation of the speedup of a two-way superscalar cpu. The problem is as follows: There is a two-way superscalar CPU with 2 ...
1
vote
1answer
27 views

Effective computation on linear data without random access

recently I've started thinking about caching problems in modern CPUs, where they struggle to adequately fetch program data (not instructions) in time, so that it can be computed further. So then I ...
-1
votes
1answer
23 views

Difference in CPU Wattage Question [closed]

If I have 2 CPU's of the same manufacturer... say AMD Both are Quad-Core, Both are rated at 3.6Ghz 1 is 100W, the other is 65W Will the one with the higher wattage out-perform the lower one and ...
1
vote
2answers
46 views

Does splitting a process across 4 terminal windows decrease the time it takes?

Basically, I using an algorithm called 'miranda' to look at miRNA targets and it only runs on a single thread. It compares everything in one file against everything in another file, produces a file as ...
1
vote
1answer
98 views

A question from Computer Organization on Peak Clock Frequency

Given below are 3 different pipelined processors: $P_1:\ 4\ stages\ with\ delays\ \ \ \ 0.6_{ms}\ \ 0.8_{ms}\ \ 0.6_{ms}\ \ 1.1_{ms}\\ P_2:\ 4\ stages\ with\ delays\ \ \ \ 2.0_{ms}\ \ 1.8_{ms}\ \ ...
2
votes
1answer
107 views

Why Instruction Decode and Register Read are in the same stage of MIPS pipeline

Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
-2
votes
3answers
238 views

Execution time of an uneven pipeline

I was trying to solve a question dealing with n instructions in an uneven pipeline with k stages. I came across a generic formula for even pipelines i.e. (k + n - 1) * clock cycle. But I feel this ...
0
votes
0answers
139 views

How are the control signals derived in the MIPS pipeline?

NOTE: Let me point out that I did try extensively to solve this on my own. The problem is that, based on that circuit, it would appear that this processor cannot jump. At best the jump instruction ...
3
votes
3answers
336 views

Difference between memory access and write-back in RISC pipeline

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline. We learned in class these following assumptions: ...
7
votes
1answer
624 views

When do structural hazards occur in pipelined architectures?

I'm looking for some relatively simple examples of when structural hazards occur in a pipelined architecture. The only scenario I can think of is when memory needs to be accessed during different ...
6
votes
2answers
234 views

Which kind of branch prediction is more important?

I have observed that there are two different types of states in branch prediction. In superscalar execution, where the branch prediction is very important, and it is mainly in execution delay rather ...