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1answer
26 views

what is the difference between memory access and data memory access?

what is the difference between memory access and data memory access? for example, here are the examples of register transfer language instructions: $R1 ←[18]$ $R2 ←[R1 +3]$ $R1 ← R1 ...
0
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0answers
15 views

Average Time for Write Through & Write Back policies

Tc -> cache updation time(per word) Tm -> main memory updation time(per word) Tb -> updation time of a block (Both policies below don't follow a strict hierarchy. i.e. if there is a miss the ...
-1
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0answers
12 views

How do one calculate Disk Trasfer Time

Q1) Given a question with z Byte track size x Byte sector size and R rpm IO time = seektime + latency time + transfer time . How to calculate the last part ? transfer time ? Q2 ) if no method to ...
1
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1answer
25 views

What is M referring to when talking about memory size( 4M x 8)

In the following paragraph its talking about memory and it throws M into the L X W of memory notation and i'm confused on how 4M = 2^22. Thanks in advance PARAGRAPH: Memory is built from random ...
3
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1answer
26 views

How can I calculate the effective bandwidth of a memory system?

I am currently doing my homework for my Computer Architecture class. One of the questions asks: A computer has a 64-bit data bus and 64-bit-wide memory blocks. The memory devices have an access ...
2
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0answers
145 views

Solving for Hit Ratio of a Theoretical Memory System

Long time lurker, first time poster. The book I am reading is William Stalling's "Operating Systems: Internals and Design Principles" Seventh Edition. Stalling's definition of hit ratio according to ...
0
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2answers
88 views

How does a hard drive knows what bit is the beginning of of a byte/word?

I'm guessing I could replace the words "hard drive" with "random access medium" but let's be more specific here. Also for the sake of this question, let's not consider SSDs. Just plain old hard-drives ...
0
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0answers
134 views

How do you calculate when effective access time is greater than cache access time?

I'm having trouble understanding how to calculate effective access time, hit ratios and cache access times. I'm unfamiliar with the concepts and would love help, or an explanation on how to solve this ...
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6answers
4k views

How does a computer determine the data type of a byte?

For example, if the computer has 10111100 stored on one particular byte of RAM, how does the computer know to interpret this byte as an integer, ASCII character, or ...
1
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0answers
46 views

Dividing/Multiplying Numbers Stored in two memory locations

I have two numbers x and y. The upper bits of x are stored at location m, while the lower bits of x are stored at location n. The upper bits of y are stored at location i, while the lower bits of y ...
2
votes
2answers
51 views

Bytes and bits conversion?

It is claimed in my textbook that In a 32-bit system, The instruction LDR r4,[r6] lets you address a logical space of 4GB. I know where the 4GB comes from, It is simply 2^32 / (1024 x 1024 x ...
-2
votes
1answer
56 views

How does the operating system set up memory boundaries? [closed]

Is there a hardware interrupt that is pre-configured by the OS or something? Try to keep the answer on the scale of a register or so. Are some special preparatory signals sent across the bridges ...
1
vote
1answer
33 views

CPU reading cycles. [closed]

Assume the CPU has 64 data lines. Then Z reading cycles will be needed to load an array of 12 double-precision floating-point numbers, each number coded in eight bytes, from the main memory into the ...
0
votes
1answer
313 views

How many bits would be needed for the byte?

The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in ...
0
votes
0answers
32 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
0
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0answers
136 views

What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
2
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0answers
256 views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
0
votes
2answers
900 views

Would it be possible to use the cloud for RAM?

I'm not sure if this is the right place to ask but I had this idea. Since the cloud can be used for storing memory, would it be possible to use it for RAM too?
2
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0answers
47 views

When there's no memory, should malloc or read/write fail?

To my surprise, I recently found out that Windows would fail a large memory allocation even if little of said memory is to actually be used, e.g. even if you don't want the swap, you better not ...
2
votes
2answers
109 views

where is all deleted data will go from memory system/internet? [closed]

where is all deleted data will go from a memory system ? if it is not deleting actually where it storing ? i am always wonder about this when we are sending something to a memory system it takes ...
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1answer
22 views

Computing vector load and stores [closed]

If $a,b,c,y$ are all scalar doubles, then $y = a\cdot b$ would result in 16 bytes from loading $a,b$ and 8 bytes for storing $y$, a total of 24 bytes transferred. Likewise, $y = a\cdot b + c$ results ...
0
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0answers
77 views

Which of the following instructions can reference a memory location that is #1000 locations from the instruction?

I am working on a question from a practice computer organization exam. The answer key to one of the questions says that both LD and ...
1
vote
2answers
724 views

average time to access a word in memory

Here is the question: Consider a computer system that has cache memory, main memory (RAM) and disk, and the operating system uses virtual memory. It takes 2 nsec to access a word from the cache, ...
0
votes
1answer
143 views

How do I build a read/write 4-nibble RAM memory system using flip flops?

Currently, I'm learning about flip flops and how it is used in RAM to store memory so I'm trying to recreate the circuitry in Logisim. I know the components I need which are address register, 4-bit ...
4
votes
3answers
832 views

Is order of bits in byte really not of concern?

What I can't wrap my head around is sentence repeated everywhere I look, that order of bits in byte is not important(not of my, as a programmer, concern). My question then is if there is possibility ...
3
votes
1answer
496 views

What is oblivious RAM and how does it work?

Could anybody explain me what exactly oblivious RAM is? I found the following explanation which makes it kind of clear to me, but I would like to get a sense of the technical aspects: Encryption ...
0
votes
1answer
257 views

Comparing random access and sequential access

Assume that we choose randomly $k$ distinct numbers $N_1$, $\dots$, $N_k$ in $\{1, \dots, k\}$ and we have a file of $k$ parts. We have these two cases : We read (or write) sequentially from part ...
1
vote
2answers
158 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
1
vote
0answers
86 views

Maximum memory accessible by the CPU [closed]

I've read multiple times (for example in some of the answers to this question http://stackoverflow.com/questions/8869563/how-much-memory-can-be-accessed-by-a-32-bit-machine) that a CPU with 32 bit ...
2
votes
2answers
158 views

Which part of the computer allocates memory in RAM?

When we declare a variable there will be a random part of memory will be allocated in RAM. Which component will allocate the memory? Is the processor or any other specific hardware doing the ...
3
votes
2answers
4k views

Word- or byte-addressable? Correct terminology

Seemingly, a byte has established itself to be 8bit (is that correct?). RAM and NOR-flash can be normally accessed on a quite granular level, but it is up to the system architecture to determine if ...
2
votes
3answers
2k views

How to determine the maximum RAM capacity for an operating system?

I was curious to know what limits the max RAM capacity for an OS while reading about microprocessors being 32-bit and 64-bit. I know that limit for 32-bit OS is 4GB and for 64-bit OS is 16 Exabytes, ...
-1
votes
1answer
171 views

How to determine the address of an element in a square matrix given the base address? [closed]

I was asked this question in examination. A square matrix $M$ of size $10 \times 10$ is stored in memory with each element requiring 4 bytes of storage. If the base address at $M[0][0]$ is $1840$, ...
1
vote
1answer
2k views

Valid-invalid bit in a process page table

Valid-invalid bit is used to indicate whether a page in a process’s page table is valid or not. Why is it needed? Does that mean that each page table has a certain minimum size, i.e. it can ...
0
votes
2answers
120 views

Valgrind: what is the difference between a store and a modify? [closed]

I am using the Vlagrind lackey tool to examine the full memory reference string of a running computer program and wonder what the difference between a "store" and a "modify" might be - and do these ...
0
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0answers
31 views

Applications affected by memory performance

I'm writing a paper on the topic of applications affected more by memory performance than processor performance. I've got a lot written regarding the gap between the two, however I can't seem to find ...
1
vote
1answer
188 views

DFA memory bandwidth

When we talk about DFA, we say that each new character from the input requires one memory access. What does that mean? This is what I think about this. Please tell me is this right? For example, I ...
1
vote
0answers
40 views

static paging vocabulary request

What is the term for an algorithm that always requests the same sequence of pages? I recall seeing this concept before buti haven't been able to find anything on Google without more specific ...
1
vote
1answer
177 views

How a program is copied to RAM from harddisk

I know that for executing a program, it should be copied to RAM. But the problem is whole of it may not be copied always. Since the size of the RAM is limited, there is mechanism called virtual ...
0
votes
1answer
3k views

Dynamic loading vs. dynamic linking?

What is the difference between dynamic loading and dynamic linking? Both systems seem to allow shared libraries, but I am struggling to differentiate between them.
3
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3answers
1k views

Finding cache block transfer time in a 3 level memory system

Following question was asked in one of entrance exams for a graduation programme. Please help me try to solve it : A computer system has an L1 cache, an L2 cache, and a main memory unity ...
3
votes
2answers
8k views

Changing from Kernel mode to User mode (and vice versa)

I am reading Operating Systems book by Galvin. Galvin explains, what are kernel & user modes, instruction privileges given for both modes & also about mode-bit. But I am interested to know how ...
3
votes
3answers
1k views

How DMA improves I/O operation efficiency?

I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. Stallings pretty well explains why Programmed I/O (CPU keeps checking the I/O module register ...
1
vote
1answer
277 views

categories of registers and and storage in them

The Wikipedia article on processor registers mentions: Address registers hold addresses and are used by instructions that indirectly access primary memory. Which addresses does this sentence ...