The tag has no wiki summary.

learn more… | top users | synonyms

-3
votes
1answer
24 views

What is the capacity of a ROM chip? [on hold]

As the capacity for RAM is given in MB, rather GBs like 256 MB, 512 MB, Now 1GB, 2GB,GB, 8GB....etc. What is the capacity that a ROM (not the Flash Memory) contains?
2
votes
0answers
26 views

When there's no memory, should malloc or read/write fail?

To my surprise, I recently found out that Windows would fail a large memory allocation even if little of said memory is to actually be used, e.g. even if you don't want the swap, you better not ...
2
votes
2answers
57 views

where is all deleted data will go from memory system/internet? [closed]

where is all deleted data will go from a memory system ? if it is not deleting actually where it storing ? i am always wonder about this when we are sending something to a memory system it takes ...
-1
votes
1answer
14 views

Computing vector load and stores

If $a,b,c,y$ are all scalar doubles, then $y = a\cdot b$ would result in 16 bytes from loading $a,b$ and 8 bytes for storing $y$, a total of 24 bytes transferred. Likewise, $y = a\cdot b + c$ results ...
0
votes
0answers
40 views

Which of the following instructions can reference a memory location that is #1000 locations from the instruction?

I am working on a question from a practice computer organization exam. The answer key to one of the questions says that both LD and ...
0
votes
2answers
92 views

average time to access a word in memory

Here is the question: Consider a computer system that has cache memory, main memory (RAM) and disk, and the operating system uses virtual memory. It takes 2 nsec to access a word from the cache, ...
0
votes
1answer
80 views

How do I build a read/write 4-nibble RAM memory system using flip flops?

Currently, I'm learning about flip flops and how it is used in RAM to store memory so I'm trying to recreate the circuitry in Logisim. I know the components I need which are address register, 4-bit ...
4
votes
3answers
808 views

Is order of bits in byte really not of concern?

What I can't wrap my head around is sentence repeated everywhere I look, that order of bits in byte is not important(not of my, as a programmer, concern). My question then is if there is possibility ...
2
votes
1answer
75 views

What is oblivious RAM and how does it work?

Could anybody explain me what exactly oblivious RAM is? I found the following explanation which makes it kind of clear to me, but I would like to get a sense of the technical aspects: Encryption ...
0
votes
1answer
155 views

Comparing random access and sequential access

Assume that we choose randomly $k$ distinct numbers $N_1$, $\dots$, $N_k$ in $\{1, \dots, k\}$ and we have a file of $k$ parts. We have these two cases : We read (or write) sequentially from part ...
0
votes
1answer
38 views

What is the correct term for “time to establish a connection” [on hold]

I don't remember what is the term for "time to establish a connection". For example in a smartphone, when I lost the wifi signal and the phone try to get mobile data connection it spends a bit of ...
0
votes
1answer
79 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
1
vote
0answers
66 views

Maximum memory accessible by the CPU [closed]

I've read multiple times (for example in some of the answers to this question http://stackoverflow.com/questions/8869563/how-much-memory-can-be-accessed-by-a-32-bit-machine) that a CPU with 32 bit ...
2
votes
2answers
121 views

Which part of the computer allocates memory in RAM?

When we declare a variable there will be a random part of memory will be allocated in RAM. Which component will allocate the memory? Is the processor or any other specific hardware doing the ...
2
votes
1answer
2k views

Word- or byte-addressable? Correct terminology

Seemingly, a byte has established itself to be 8bit (is that correct?). RAM and NOR-flash can be normally accessed on a quite granular level, but it is up to the system architecture to determine if ...
-1
votes
1answer
73 views

How to determine the address of an element in a square matrix given the base address? [closed]

I was asked this question in examination. A square matrix $M$ of size $10 \times 10$ is stored in memory with each element requiring 4 bytes of storage. If the base address at $M[0][0]$ is $1840$, ...
1
vote
1answer
947 views

Valid-invalid bit in a process page table

Valid-invalid bit is used to indicate whether a page in a process’s page table is valid or not. Why is it needed? Does that mean that each page table has a certain minimum size, i.e. it can ...
0
votes
2answers
98 views

Valgrind: what is the difference between a store and a modify? [closed]

I am using the Vlagrind lackey tool to examine the full memory reference string of a running computer program and wonder what the difference between a "store" and a "modify" might be - and do these ...
0
votes
0answers
29 views

Applications affected by memory performance

I'm writing a paper on the topic of applications affected more by memory performance than processor performance. I've got a lot written regarding the gap between the two, however I can't seem to find ...
1
vote
0answers
40 views

static paging vocabulary request

What is the term for an algorithm that always requests the same sequence of pages? I recall seeing this concept before buti haven't been able to find anything on Google without more specific ...
1
vote
1answer
131 views

How a program is copied to RAM from harddisk

I know that for executing a program, it should be copied to RAM. But the problem is whole of it may not be copied always. Since the size of the RAM is limited, there is mechanism called virtual ...
0
votes
1answer
2k views

Dynamic loading vs. dynamic linking?

What is the difference between dynamic loading and dynamic linking? Both systems seem to allow shared libraries, but I am struggling to differentiate between them.
1
vote
3answers
949 views

Finding cache block transfer time in a 3 level memory system

Following question was asked in one of entrance exams for a graduation programme. Please help me try to solve it : A computer system has an L1 cache, an L2 cache, and a main memory unity ...
3
votes
1answer
4k views

Changing from Kernel mode to User mode (and vice versa)

I am reading Operating Systems book by Galvin. Galvin explains, what are kernel & user modes, instruction privileges given for both modes & also about mode-bit. But I am interested to know how ...
3
votes
3answers
854 views

How DMA improves I/O operation efficiency?

I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. Stallings pretty well explains why Programmed I/O (CPU keeps checking the I/O module register ...
1
vote
1answer
192 views

categories of registers and and storage in them

The Wikipedia article on processor registers mentions: Address registers hold addresses and are used by instructions that indirectly access primary memory. Which addresses does this sentence ...