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0answers
16 views

restoring ancient hardware [on hold]

I find it a shame to see so many systems today being sent to recycle yards or landfills because they are not able to function on a comparable level as other systems today.... I am curious if it may ...
0
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2answers
27 views

Increasing Cache Line and Programs with bad Spatial Locality

I'm reading on caches and I'm feeling a bit lost with spatial locality. From my understanding, increasing the cache line with a program that has high spatial locality reduces the miss rate. But for ...
1
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1answer
29 views

How does the OS Scheduler give/take control of HW?

Imagine a uniprocessor system with a simple operating system with non-threaded processes and basic virtual memory (paging, no segmentation, no replacement to disk, etc). Now assume a simple ...
2
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1answer
39 views

How does RAID-5 algorithm locate the right device?

Please consider the following diagram of a RAID-5 array (Ignore the gray background): Now, given a logical address, how can one return the device number (0-3)? For example, ...
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7answers
5k views

Is a computer without RAM, but with a disk, equivalent to one with RAM?

Memory is used for many things, as I understand. It serves as a disk-cache, and contains the programs' instructions, and their stack & heap. Here's a thought experiment. If one doesn't care about ...
1
vote
1answer
22 views

Mapping several memories to one address space

I am trying to understand deeply how memories work in computers, and I faced the next difficulty. Let's say we have a device with two memory chips but only one address space (for example, 0x00000000 ...
2
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1answer
39 views

How does a register remember value?

So I am studying this great book, and Chapter $3.1$ is about registers. Quoting from this book / chapter: A register is a storage device that can "store" or "remember" a value over time, ...
3
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2answers
53 views

Why is word-addressable the exception, not the rule?

As stated on Wikipedia: Most modern computers are byte-addressable instead of word-addressable. Why is this case? Since the CPU processes words (of predominantly 64 bits or 8 bytes) now, ...
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0answers
13 views

Calculating Unique Addresses In Word Addressable Memory

According to a textbook assigned for my class, if I have memory that is 4M X 16, to address this memory (assuming word addressing), we need to be able to uniquely identify $2^{12}$ different items, ...
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votes
1answer
73 views

Deleted data remains on a disk until? [closed]

I am little bit confused between the two answers below. What is the exact answer of this question? My query is, "Deleted data remains on a disk until...?" The data is overwritten; The recycle bin ...
1
vote
2answers
51 views

Computer cache - data removing

I am programming CPU cache simulator and I am supposed to implement removing of entries. I will not use LRU but just random. I am not really clear, when should I call the removing function? When ...
1
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0answers
11 views

Would there be any advantage to using transitors of more than two states? [duplicate]

Binary is the result of using the simplest possible building blocks to hold memory, transistors, entities that can be switched between two states, on or off. We took that idea and ran with it, and it ...
0
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0answers
14 views

What will be the seek time if I want read two track one after the other?

I read the disk scheduling and the came across a question saying that the seek time is 32ms. And one track contain 32 Mb data. We have to read 64Mb from the disk which is stored in contiguous manner. ...
3
votes
1answer
57 views

How can I calculate the effective bandwidth of a memory system?

I am currently doing my homework for my Computer Architecture class. One of the questions asks: A computer has a 64-bit data bus and 64-bit-wide memory blocks. The memory devices have an access ...
-1
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2answers
107 views

/How/ is the machine code within the CPU physically implemented; /why/ precisely does this work; and /where/ is it stored? [closed]

I understand the concept that the CPU's machine code is what translates the binary input into commands, and then executes these commands, many billion times per second. I can understand how, given ...
1
vote
1answer
74 views

Why is data fragmentation not possible on main memory (RAM)?

I am wondering why data fragmentation is a problem on main memory. On a software level, virtual addresses are used anyway. So why can one address space not be split up into multiple segments, like a ...
0
votes
1answer
27 views

Where is the reorder buffer (ROB)? [closed]

I just wonder where the ROB is in. Is ROB in the memory or cache or where??
1
vote
1answer
105 views

Relationship between RAM size and 32-bit vs 64-bit word size

I know that x86 supports only 4GB of RAM, and that switching to x64 greatly increases the size of RAM you can use, but I don't understand why. Why is the maximum supported ram size related to whether ...
2
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2answers
42 views

Caches and reading a PDF

I am currently learning about caches in Systems class, and I had a few doubts about what exactly happens when a Computer reads a PDF. This is the sequence that happens in my mind: The CPU checks if ...
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2answers
61 views

What is a swap-with-memory instruction?

I am reading an article on algorithms for parallel computing and came across the following sentence. What do they mean by a swap-with-memory instruction? Our algorithm provides reasonable latency ...
1
vote
1answer
47 views

Does the databus size matter for determining the range of the memory addresses?

If you have byte addressable memory, does it matter if you have a 32 bit or 64 bit databus for the range of the memory addresses for the words of the memory? E.g. : Assume a 32-bit word. If you have ...
2
votes
1answer
174 views

How can i compute tag-index-displacement bits of an address if cache size is not a power of two?

How can i compute tag-index-displacement bits from an address if cache size is not a power of two? Intuitively, i would be inclined to think that i can not directly indicate which bits of the address ...
2
votes
1answer
147 views

What if block sizes are not equal among caches?

In all the books, packets of slides and similar I read, cache miss is always explained by assuming that blocks of different caches (or cache and RAM) are always of the same size. It's pretty clear how ...
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2answers
98 views

How does a hard drive knows what bit is the beginning of of a byte/word?

I'm guessing I could replace the words "hard drive" with "random access medium" but let's be more specific here. Also for the sake of this question, let's not consider SSDs. Just plain old hard-drives ...
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6answers
4k views

How does a computer determine the data type of a byte?

For example, if the computer has 10111100 stored on one particular byte of RAM, how does the computer know to interpret this byte as an integer, ASCII character, or ...
2
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0answers
53 views

How does the Spark M7 “Concurrent Fine-grain Memory Migration” benefit a garbage collector?

Sun has been making a lot of noise about the Spark M7 and its inbuilt support for the java garbage collector. However there seem to be very little easy to find information about it. Please can ...
3
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0answers
37 views

References on memory subsystems

I took a typical computer architecture class a long time ago as an undergrad and since then I've done a fair amount of low-level systems programming down to the assembly level and worked on OS ...
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votes
1answer
53 views

Cache question help me here? [closed]

Quantify the effect in performance which comes from using the cache ,if We are going to use a program which is made from 500 machine instructions ,from which 100 are in a cycle which is executed 25 ...
0
votes
1answer
70 views

RAW Data Hazard resolution

Let's consider the following MIPS (using pipelined arch.) assembly code: lw r1,0(r2) sub r4, r1, r6 and r6, r1, r7 or r8, r1, r9 the r1 value used in the second ...
2
votes
3answers
116 views

Who converts binary/machine code to electrical signals and how?

I went through lots of blogs and posts but could not exactly figure out how the machine code is converted to electrical signals? Any software program is compiled to machine code which is nothing but ...
0
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0answers
33 views

Is this cache entry a hit or a miss? [duplicate]

The Problem: A CPU produces the following sequence of read addresses in hex. Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address produces a hit or ...
2
votes
0answers
329 views

Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
2
votes
2answers
635 views

Advantage of byte addressable memory over word addressable memory

What is the reason that almost all computers (besides some DSPs) use byte addressable memory? With byte addressable memory and a 32 bit address you can have 4GB while with word addressable memory you ...
2
votes
2answers
125 views

where is all deleted data will go from memory system/internet? [closed]

where is all deleted data will go from a memory system ? if it is not deleting actually where it storing ? i am always wonder about this when we are sending something to a memory system it takes ...
0
votes
1answer
51 views

How is electricity brought to the transistors? [closed]

I feel like my knowledge of computer science is being hindered by this one concept. I understand the concepts of transistors and how a flow of electricity can turn a transistor on or off, and with ...
0
votes
1answer
219 views

speed, cost and capacity tradoff

I'm reading William Stalling's Operating System Design and internals. Talking about memory, the following tradeoff was introduced: As might be expected, there is a tradeoff among the three key ...
2
votes
1answer
105 views

What is this trapezoid-shaped logic component?

This is from http://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/Ch05.pdf , slide 9. From this diagram, I recognize 0001 as the opcode, which corresponds to the ADD instruction. I recognize 011, ...
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2answers
81 views

Are hardware specs relevant in software performance comparisons?

I notice occasionally in blogs or articles comparing different languages, algorithms, etc. that the author will divulge info about the processor used in the testing. Is this meaningful? Shouldn't ...
1
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2answers
998 views

average time to access a word in memory

Here is the question: Consider a computer system that has cache memory, main memory (RAM) and disk, and the operating system uses virtual memory. It takes 2 nsec to access a word from the cache, ...
2
votes
5answers
467 views

How can a CPU access more memory locations than 2^wordsize?

I noticed that CPU's like the 8086 and especially the 8080 have the ability to access more memory than what one would normally assume. The 8080, for example, has an 8-bit word size but can use a ...
0
votes
1answer
169 views

How do I build a read/write 4-nibble RAM memory system using flip flops?

Currently, I'm learning about flip flops and how it is used in RAM to store memory so I'm trying to recreate the circuitry in Logisim. I know the components I need which are address register, 4-bit ...
0
votes
1answer
248 views

Maximum I/O Data Transfer if DMA is used

I was reading lecture notes of Universiti Malaysia Perlis when I am came across following question: A computer consists of a CPU and an I/O device $D$ connected to main memory $M$ via a shared ...
-1
votes
1answer
224 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
0
votes
1answer
166 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
4
votes
1answer
584 views

What is oblivious RAM and how does it work?

Could anybody explain me what exactly oblivious RAM is? I found the following explanation which makes it kind of clear to me, but I would like to get a sense of the technical aspects: Encryption ...
1
vote
1answer
376 views

Compute the Hamming code with odd parity for the memory word 1101 1001 0001 1011

This is the problem I have: Compute the Hamming code with odd parity for the memory word 1101 1001 0001 1011 (2 pts.). In your solution, mark the parity bits as in the following example, where ...
-1
votes
2answers
2k views

Calculating disk seek times

I have a system where disk requests come to a disk drive for cylinders in the order 10, 22, 20, 2, 40, and 38 at a time when the disk drive is reading from cylinder 20. The seek time is 6ms per ...
0
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2answers
109 views

Addressing mode

I'm studying for an exam called Computer Fundamental, and started taking some previous exam but the given documents i had is way inadequate to solve all the question mentioned, like this one : ...
0
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0answers
65 views

Roles of the Memory Management Unit

I know that the first instruction stored in BIOS is "mapped" to memory address 0, and that a signal on the reset pin to the microprocessor causes this instruction to be fetched, beginning the POST and ...
0
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1answer
153 views

Possible valid and invalid codewords

I have already read different things about hamming distance, hamming code, detection and correction of memory errors, but I am still not understanding many things. I know that the hamming distance ...