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5 views

Understanding how EIP (RIP) register works? [migrated]

I'm a complete novice to computer architecture and the low level stuff that happens at the processor/memory level. I'll start by saying that. What i've done with computers has pretty much always been ...
-2
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0answers
42 views

Direct Mapped Cache: Number of blocks replaced

I am working on this problem: Starting from power on, the following byte-addressed cache references are recorded. ...
-1
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1answer
15 views

Direct Cache Mapping - Determine Tag Size

In the following direct cache map, there is a list of 32-bit memory address references, given as word addresses. I gathered that the index size is 3 bit and there is no offset. However, I used 4 bits ...
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0answers
18 views

Direct Cache Mapping Hit Or Miss

I am have a difficult time understanding when a direct map cache is a hit or a miss. My understanding is that when and index matches, but a tag doesn't it is still a miss but the new tag then takes ...
2
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1answer
40 views

What is oblivious RAM and how does it work?

Could anybody explain me what exactly oblivious RAM is? I found the following explanation which makes it kind of clear to me, but I would like to get a sense of the technical aspects: Encryption ...
0
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0answers
14 views

Is current hardware adequate for neural networks ? Are there more adequate hardware?

If you have a large neural network and you use more than 10 cores, it will be limited by the fact each core will need to read/write data that it can't access fast enough. I've read about some samsung ...
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1answer
41 views

Compute the Hamming code with odd parity for the memory word 1101 1001 0001 1011

This is the problem I have: Compute the Hamming code with odd parity for the memory word 1101 1001 0001 1011 (2 pts.). In your solution, mark the parity bits as in the following example, where ...
-1
votes
1answer
50 views

Calculating disk seek times

I have a system where disk requests come to a disk drive for cylinders in the order 10, 22, 20, 2, 40, and 38 at a time when the disk drive is reading from cylinder 20. The seek time is 6ms per ...
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2answers
41 views

Addressing mode

I'm studying for an exam called Computer Fundamental, and started taking some previous exam but the given documents i had is way inadequate to solve all the question mentioned, like this one : ...
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0answers
30 views

Roles of the Memory Management Unit

I know that the first instruction stored in BIOS is "mapped" to memory address 0, and that a signal on the reset pin to the microprocessor causes this instruction to be fetched, beginning the POST and ...
0
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1answer
32 views

Possible valid and invalid codewords

I have already read different things about hamming distance, hamming code, detection and correction of memory errors, but I am still not understanding many things. I know that the hamming distance ...
2
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2answers
93 views

Spatial Locality in Cache - Which addresses are loaded?

I don't quite understand the concept of spatial locality in cacheing. I understand that on a cache miss, not only the specific address we want is loaded into the cache, but also "nearby addresses" are ...
6
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1answer
55 views

Writing a multitasking operating system for a processor without MMU

I've been thinking of writing a hobby operating system for some of the ARM processors. There are many popular single-board computers with ARM MPU, so I simply wanted to purchase one of those (choosing ...
1
vote
1answer
50 views

Back invalidation to maintain inclusion in inclusive cache

For an L2 cache that is strictly inclusive of the L1 cache, if a block to be evicted is also present in L1, then back invalidation is required to maintain the inclusion property. I am interested in ...
1
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2answers
82 views

How is data written to RAM

From my understanding(correct me if I am wrong) when I read data from RAM memory it is copied into processor cache and than it is copied into register to be used by the processor. When I create data ...
1
vote
2answers
172 views

What is the maximum directly adddressable memory capacity?

This is taken from OPERATING SYSTEMS: INTERNALS AND DESIGN PRINCIPLES by WILLIAM STALLINGS Consider a 32-bit microprocessor composed of 2 fields: first byte contains the opcode and remainder an ...
2
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3answers
380 views

Is a supercomputer more powerful than the total of all the world's computers in 2004?

The supercomputer I am researching has 2.2 petaflops and boasts total memory of 1000 terabytes and disk space of 23.5 petabytes. Is this more computing power than the total of the entire worlds ...
2
votes
2answers
267 views

Why do Computers use Hex Number System at assembly language?

Why do computer use Hex Number System at assembly language? Why don't they use any other number system like binary, octal, decimal? What thing forced computer designer to use hex system at assembly? ...
2
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1answer
69 views

Why do servers use ECC memory? [closed]

I understand that ECC checks for errors and corrects them automatically without the knowledge of the operating system or user. I don't understand however why servers often use ECC memory?
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0answers
53 views

Maximum memory accessible by the CPU [closed]

I've read multiple times (for example in some of the answers to this question http://stackoverflow.com/questions/8869563/how-much-memory-can-be-accessed-by-a-32-bit-machine) that a CPU with 32 bit ...
-1
votes
1answer
201 views

How to find out memory size by hex ranges?

so I am a bit confused here. I read a memory-map ranging from certain hex values and I'm trying to find out how large RAM is by it. Here's the code: ...
2
votes
2answers
89 views

Which part of the computer allocates memory in RAM?

When we declare a variable there will be a random part of memory will be allocated in RAM. Which component will allocate the memory? Is the processor or any other specific hardware doing the ...
-1
votes
1answer
222 views

CPU bit, its cache line, the bus between memory and CPU, and its registers?

Should the size of its cache line, the width of bus between memory and CPU, and the size of its registers be all equal to the CPU bit? Is CPU bit determined by the size of its cache line, the width ...
2
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0answers
79 views

How does hardware interrupt work on a physical layer

I'm a newbie in computer science and would to understand how hardware interrupts work at the physical layer. I ask my question considering a specific example. When packet arrives at the network ...
0
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0answers
48 views

What is the differences between address subdivision and block subdivision

I'm learning for the final exam of Computer System subject, Chapter 5 Large and Fast: Exploiting Memory Hierarchy in the Computer Organization and Design There are 2 types of subdivision that is ...
12
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3answers
394 views

Parallelising random reads seems to work well — why?

Consider the following very simple computer program: for i = 1 to n: y[i] = x[p[i]] Here $x$ and $y$ are $n$-element arrays of bytes, and $p$ is an ...
0
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1answer
96 views

In cache addressing, what value is placed in the offset field?

There is a 64 KB 1-word cache, and a word is 32 bits. From that I can derive that the length of the tag field is 16 bits, the length of index field is 14 bits, and, as my professor taught me, there ...
5
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2answers
136 views

How do computers compute?

This is a kind of follow-up to a question I asked on superuser, where I asked for the definitions of a 'distinghuisable state' and a 'memory cell'. My questions where properly answered, but I was ...
1
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0answers
69 views

Drawing the Design of an SRAM chip

I have come across a question that I am having quite a hard time with. I am to draw a design of an SRAM chip with an organization of 2M*128 SRAM that uses 1K*1K arrays of D latches. And then the ...
-1
votes
1answer
83 views

General question about how CPUs send and receive data/bytes to hardware?

Realize I didn't mention x86 or any more details to make this non-specific to any platform, but to just get a general idea of how this is done(this is also a long question with a lot of details). I ...
3
votes
1answer
180 views

Why we need EEPROM in this micro-controller

PIC16F887 Block Diagram According to the block diagram above, since we already have Program Memory, which may be used to store our program, why should we still need EEPROM? What is it for?
3
votes
3answers
597 views

How DMA improves I/O operation efficiency?

I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. Stallings pretty well explains why Programmed I/O (CPU keeps checking the I/O module register ...
2
votes
1answer
128 views

Computer Architecture-3 level RAM hierarchy

In all computer architecture books we study that Cache memory could be divided into 3 levels (L1,L2 and L3) and its very beneficial to do so. Why don't we use the same approach in case of main memory ...
2
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1answer
89 views

Where do these DRAM row/column calculations come from?

Let r be the number of rows in a DRAM array, and c be the number of columns. Apparently, DRAM with organization 16x1 requires least pins when r = c = 4 because fewer address bits are required to ...