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-1
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1answer
22 views

How to find out memory size by hex ranges?

so I am a bit confused here. I read a memory-map ranging from certain hex values and I'm trying to find out how large RAM is by it. Here's the code: ...
1
vote
2answers
58 views

Which part of the computer allocates memory in RAM?

When we declare a variable there will be a random part of memory will be allocated in RAM. Which component will allocate the memory? Is the processor or any other specific hardware doing the ...
0
votes
1answer
36 views

CPU bit, its cache line, the bus between memory and CPU, and its registers?

Should the size of its cache line, the width of bus between memory and CPU, and the size of its registers be all equal to the CPU bit? Is CPU bit determined by the size of its cache line, the width ...
2
votes
0answers
49 views

How does hardware interrupt work on a physical layer

I'm a newbie in computer science and would to understand how hardware interrupts work at the physical layer. I ask my question considering a specific example. When packet arrives at the network ...
0
votes
0answers
32 views

What is the differences between address subdivision and block subdivision

I'm learning for the final exam of Computer System subject, Chapter 5 Large and Fast: Exploiting Memory Hierarchy in the Computer Organization and Design There are 2 types of subdivision that is ...
12
votes
3answers
357 views

Parallelising random reads seems to work well — why?

Consider the following very simple computer program: for i = 1 to n: y[i] = x[p[i]] Here $x$ and $y$ are $n$-element arrays of bytes, and $p$ is an ...
0
votes
1answer
44 views

In cache addressing, what value is placed in the offset field?

There is a 64 KB 1-word cache, and a word is 32 bits. From that I can derive that the length of the tag field is 16 bits, the length of index field is 14 bits, and, as my professor taught me, there ...
5
votes
2answers
119 views

How do computers compute?

This is a kind of follow-up to a question I asked on superuser, where I asked for the definitions of a 'distinghuisable state' and a 'memory cell'. My questions where properly answered, but I was ...
1
vote
0answers
50 views

Drawing the Design of an SRAM chip

I have come across a question that I am having quite a hard time with. I am to draw a design of an SRAM chip with an organization of 2M*128 SRAM that uses 1K*1K arrays of D latches. And then the ...
-1
votes
1answer
73 views

General question about how CPUs send and receive data/bytes to hardware?

Realize I didn't mention x86 or any more details to make this non-specific to any platform, but to just get a general idea of how this is done(this is also a long question with a lot of details). I ...
3
votes
1answer
151 views

Why we need EEPROM in this micro-controller

PIC16F887 Block Diagram According to the block diagram above, since we already have Program Memory, which may be used to store our program, why should we still need EEPROM? What is it for?
3
votes
3answers
463 views

How DMA improves I/O operation efficiency?

I am reading Computer Architecture & Organization by William Stallings to understand I/O operations. Stallings pretty well explains why Programmed I/O (CPU keeps checking the I/O module register ...
1
vote
1answer
103 views

Computer Architecture-3 level RAM hierarchy

In all computer architecture books we study that Cache memory could be divided into 3 levels (L1,L2 and L3) and its very beneficial to do so. Why don't we use the same approach in case of main memory ...
2
votes
1answer
44 views

Where do these DRAM row/column calculations come from?

Let r be the number of rows in a DRAM array, and c be the number of columns. Apparently, DRAM with organization 16x1 requires least pins when r = c = 4 because fewer address bits are required to ...