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2
votes
1answer
40 views

How does OS know the physical address of a process' first memory page?

If I have a program, its instructions are stored on the hard drive. When I double-click the executable the pages of memory for this process must get loaded in to RAM. However, for the pages to get ...
0
votes
1answer
37 views

How is heap memory allocated to a process?

I want to better understand how OS provides heap memory to a process. Here by heap memory I mean the memory allocated dynamically, say by call to malloc. When a ...
0
votes
1answer
25 views

In Pagination, how does the S.O. knows where the page is in secondary Memory?

So every process has its own Page Table, the page table references the frame where the page is in physical memory and also has a valid-invalid bit that tells whether it is in physical memory or in ...
3
votes
1answer
45 views

Session Memory in the Windows Kernel

While reading the paper Effective Data-Race Detection for the Kernel by John Erickson and Madanlal Musuvathi. I was stuck on a slightly tricky sentence. "Similarly, a range of kernel-address space, ...
1
vote
1answer
45 views

Maximum amount of memory that can be allocated to a process

DISCLAIMER: The following scenario was taken from an assignment I got in a OS course I'm taking, and it arose a lot of question marks in my head. However non of the questions asked by myself here ...
2
votes
2answers
62 views

How to filter a very, very large file

I have a very large unsorted file, 1000GB, of ID pairs ID:ABC123 ID:ABC124 ID:ABC123 ID:ABC124 ID:ABC123 ID:ABA122 ID:ABC124 ID:ABC123 ID:ABC124 ID:ABC126 I would like to filter the file for ...
0
votes
0answers
160 views

size of memory in 64-bit computer system

I'm new here, a brief intro, I'm a student majoring in comp-sci. Right now I'm having a bit confusion to answer one of my assignment, it is about system paging. I want to know how do I able to know ...
2
votes
3answers
45 views

Does exploiting a spatial Locality in Cache always leads to a lower miss rate?

I've read that, incorporating many words(spatial locality) per cache blocks leads to lower miss rate. Is it the case always? One possibility of such approach is to make a single cache block of size ...
0
votes
0answers
27 views

Implementing/approximating Belady's OPT for multithreaded environments (papers?)

I have the memory reference string for a multithreaded application and want to run this through a simulator which implements/approximates Belady's OPT page replacement algorithm. But what is the best ...
7
votes
1answer
92 views

Are there any garbage collectors that take into account paging?

Garbage collections have to visit all objects that are alive, so as to find the memory that can be reclaimed. (Having many generations’ just delays this a bit) All things being equal, it is ...
1
vote
1answer
20 views

What memory locations will the CPU fetch instructions from with instruction length of 16bits

While reading Stallings OS Internals and Design, I run into problem. Here is example from the book. For example, consider a simplified computer in which each instruction occupies one 16-bit word ...
1
vote
1answer
36 views

Qubits Related to RAM?

I read in this article that the amount of bits that can be emulated by a certain number of qubits is 2^(number of qubits). This is because each qubit can be in one of 2 states after it collapses, and ...
1
vote
2answers
69 views

Which part of the computer allocates memory in RAM?

When we declare a variable there will be a random part of memory will be allocated in RAM. Which component will allocate the memory? Is the processor or any other specific hardware doing the ...
0
votes
0answers
15 views

Instruction Set Architecture- Question [duplicate]

So this is a homework question but I have some solution and I am just confused, so a detailed example or help would be nice. You are designing the instruction set for a new type of computer. The ...
-1
votes
1answer
240 views

Instruction Set Architecture (ISA) design

Yes, this is a homework question, I've tried working it out and was hoping I could get pointed in the right direction. Here's the question: You are designing the instruction set for a new type of ...
2
votes
1answer
708 views

Word- or byte-addressable? Correct terminology

Seemingly, a byte has established itself to be 8bit (is that correct?). RAM and NOR-flash can be normally accessed on a quite granular level, but it is up to the system architecture to determine if ...
-1
votes
1answer
90 views

Does virtual address space resides in virtual memory?

I have several confusion like : Does virtual address space resides in virtual memory ? Does each process has its own virtual address space like each process has its own virtual memory and own page ...
-1
votes
1answer
64 views
0
votes
1answer
192 views

Size of address registers and data registers in relation with memory size

Suppose that a processor can address directly up to 4 Gigabyte main memory and can operate words with size 32 bit. Find how big should be the size of the "MAR" (memory address registers), "MDR" ...
0
votes
0answers
139 views

What determines a hit/miss with cache memory?

I was taught that when a reference is mapped to a cache block, X, for the first time, the word is stored in the cache block, bearing a tag and index that helps identify it for future reads. Then, ...
2
votes
2answers
274 views

What is “memory coalescing”?

I came to know that the graphic processing unit have something called memory coalescing. On reading on it I was not clear on the topic. Is this any way related to Memory Level Parallelism. I have ...
-1
votes
1answer
65 views

processes response time confusion

An OS contains 10 identical processes that were initiated at the same time.Each process contains 15 identical requests. Each request consume 20 msec of CPU time.A request is followed by an I/O ...
0
votes
1answer
686 views

Understanding the basic concepts in memory organisation

(Before actually proceeding to the question, I want to confess that this is a homework question, please do consider it and help me in improving my understanding a bit more.) I have recently started ...
4
votes
3answers
218 views

What does “deterministic” mean in the context of memory management?

At the time of writing, Wikipedia describes determinism as: "a deterministic algorithm is an algorithm which, given a particular input, will always produce the same output, with the underlying ...
2
votes
2answers
52 views

What does “prompt collection” mean in the context of memory management?

I often see people assert that reference counting techniques such as shared_ptr in C++ provide prompt collection (e.g. here and here) but I am not sure what exactly ...
1
vote
0answers
58 views

Drawing the Design of an SRAM chip

I have come across a question that I am having quite a hard time with. I am to draw a design of an SRAM chip with an organization of 2M*128 SRAM that uses 1K*1K arrays of D latches. And then the ...
1
vote
0answers
516 views

want to know concept behing Multilevel paging

In order to use large size page table hierarchical paging is done . In case of two level page table scheme . for : logical address space - 32bit - $2^32$ page size - 4kb i.e $2^12$ It is mentioned ...
4
votes
1answer
440 views

Despite it is so important, why don't computer science departments offer a class named “memory management”? [closed]

I don't understand why computer science departments don't offer a class named memory management? I see that most of the problems encountered in computer science are about memory management concepts. ...
1
vote
1answer
92 views

How a program is copied to RAM from harddisk

I know that for executing a program, it should be copied to RAM. But the problem is whole of it may not be copied always. Since the size of the RAM is limited, there is mechanism called virtual ...
1
vote
1answer
1k views

Hierarchical Paging

Suppose I have a system with 32-bit logical and 16-bit physical address spaces, and the page size is 512 bytes. For simplicity, ignore the valid/invalid bits in the page table. How many sections will ...
1
vote
2answers
800 views

Given the logical address, how to extract the page number?

I am studying Computer Systems. I have th following question and its answer: Given the logical address 0xAEF9 (in hexadecimal) with a page size of 256 bytes, what is the page number? ...
2
votes
1answer
1k views

What is the difference between a 'page' or memory and a 'frame' of memory?

WP has a adequate discussion of paging, which I think I understand.. However I am confused by the articles repeated use of the term Page Frame. I thought frames and pages were different things. ...
0
votes
1answer
60 views

How Does Dynamic Heap Storage Have Something to Do with Heap?

There are three typical ways to allocate memory for programs: static, stack and dynamic heap. However, when I look at the implementation of dynamic heap memory allocation from wikipedia , what I found ...
0
votes
2answers
5k views

How to work out physical address corresponding to logical address?

I am looking to calculate the physical address corresponding to a logical address in a paging memory management scheme. I just want to make sure I am getting the calculation right, as I fear I could ...
2
votes
2answers
273 views

Handling untrusted string input in printf in C [closed]

I stumbled upon the MSDN Best Practices for Code Review. Under the section “Untrusted Inputs”, I found following which I didn't understand properly. Why is the following considered safe? ...
2
votes
1answer
180 views

Processes and Segmentation

The following problem was on my final and in Gate 2006, but I don't understand how to solve it: Different methods of memory management have different overheads: ...
1
vote
2answers
2k views

How does increasing the page size affect the number of page faults?

If we let the physical memory size remain constant, What effect does the size of the page have on the number of frames? What effect does the number of frames have on the number of page faults? ...
4
votes
1answer
1k views

Program compilation and execution flow

I was studying operating system concepts from Silberschatz, Galvin and Gagne's book (sixth edition) and I have some questions about the flow of execution of a program. A figure explains the processing ...
5
votes
1answer
105 views

Are compilers able to detect alternating accesses to arrays and interleave them in memory?

Is it possible to design a compiler which optimizes a loop in which arrays are accessed in alternate fashion? For example like this: ...
8
votes
3answers
265 views

Applying algorithms on large data

Is there any book or tutorial that teaches us how to efficiently apply the common algorithms (sorting, searching, etc.) on large data (i.e. data that cannot be fully loaded into main memory) and how ...
2
votes
0answers
230 views

Queue that can sort by multiple priorities?

I have a high interest in priority-queues (E.g., see my answers on: Does there exist a priority queue with $O(1)$ extracts?), and was wondering if there is a priority-queue or similar data-structure ...
9
votes
1answer
2k views

Swap space management during pure demand paging

The following is a doubt that I came across while doing a OS home assignment - however, it seems more concept-based than a straightforward coding question, so IMHO I don't think the homework tag is ...
2
votes
2answers
225 views

Equality testing of arrays and integers in a procedural language

In terms of references and their implementation on the heap and the stack, how is equality testing for arrays different from that for integers? This is to do with Java programming, if you have a ...