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1
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0answers
18 views

Clock variant of the Second-Chance page-replacement Algorithm vs. standard Second-Chance Algorithm

A sample question for my upcoming Operating Systems exam is: Under which circumstances would the clock variant [of the second-chance algorithm] be preferred over the standard second-chance ...
-2
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1answer
26 views

Need help with a Virtual Address translation question [on hold]

I'm trying to find out how many bits are used in the virtual address for the TLB index given the following: The page size for a virtual memory system is 8KB The instruction TLB is direct-mapped with ...
16
votes
4answers
3k views

How do garbage collectors avoid stack overflow?

So I was thinking about how garbage collectors work and I thought of an interesting issue. Presumably garbage collectors have to traverse all structures in the same way. They can't know weather they ...
0
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0answers
5 views

what exactly is present in CMOS when system is turned on for first time? [migrated]

also how does cmos gets all the hardware information, parameters and stores them? Does Bios writes them into CMOS or some other hardware? Bios has facility to do POST. Is this POST anyhow related to ...
0
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1answer
23 views

How does cpu fetch active program data (using virtual address) from storage when there is a page fault?

I read that cpu generates virtual address and using the same mmu translates to physical address and then fetches the data from RAM. But when there is a page fault, the data is fetched from the HDD(or ...
0
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0answers
8 views

How to find maximum size user-space main memory that can be supported?

I can't figure out how to find maximum size of user space main memory. I have this data: 64-bit computer system that uses pure paging with 16KB page size, if each page table entry is 4 bytes ...
0
votes
1answer
29 views

Main memory to cache mapping? [on hold]

I need some advice for the third item (c) in the following question: Consider a computer with a byte-addressable memory. A 32-bit memory address is divided as follows for cache processing. ...
-1
votes
0answers
34 views

How large a frame size do I need to require 3 levels of paging?

If I have 64bit addressing that uses paging, and if frame sizes are always a power of 2, then how large of a frame size do I need which would require me to use a three-level page table? I know that ...
3
votes
1answer
52 views

When was the terminology *tracing collector* introduced to denote both mark-and-sweep and copy collectors

Automatic storage reclamation, aka garbage collection, comes in two main families, sometimes cooperating: the reference count collectors and the tracing collectors. I may develop specifics of each ...
2
votes
5answers
106 views

How can a CPU access more memory locations than 2^wordsize?

I noticed that CPU's like the 8086 and especially the 8080 have the ability to access more memory than what one would normally assume. The 8080, for example, has an 8-bit word size but can use a ...
0
votes
1answer
55 views

Binary digit problem?

Question: If a system has $32k$ bytes and each such byte has unique address(so $32k$ addresses), what is the smallest possible bits that can be use by every byte for the address ? All the bytes ...
0
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1answer
25 views

Can this question be solved without knowing the Page Table Entry?

I'm preparing for the exams and this question came up - Consider a machine with $64MB$ physical memory and a $32$-bit virtual address space. If the page size is $4KB$, what is the approximate size ...
10
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5answers
256 views

Why is the object destructor paradigm in garbage collected languages pervasively absent?

Looking for insight into decisions around garbage collected language design. Perhaps a language expert could enlighten me? I come from a C++ background, so this area is baffling to me. It seems ...
0
votes
1answer
59 views

Size of framebuffer lookup table [closed]

If the frame buffer has 8 bits per pixel and 8 bits are allocated for each of the R, G, B components, what would be the size of the lookup table? a) 24 bytes b) 1024 bytes ...
-2
votes
1answer
17 views

Why we need tagbits when we already have indexbit and offset?

I was watching a lecture and got confused at one point when professor said that to distinguish between two addresses having same values of offset as well as index bit we need tag.Why we need tag ? for ...
3
votes
1answer
42 views

Best design of a software controlled page table: to echo the TLB?

I am building some simple system software for the Microblaze FPGA (actually being run on OVPsim at least for now). The system is to experiment with various memory management regimes. The first ...
0
votes
2answers
103 views

Operating System Paging concept

I am quoting a paragraph from the book "Operating System Principles" by Galvin. Usually, each page-table entry is 4 bytes long, but that size can vary as well. A 32-bit entry can point to one of ...
1
vote
1answer
27 views

Role of the MMU in a Page Fault Swap

When a virtual memory address outside the range of loaded into physical RAM is referenced and a page fault occurs, does the Memory Management Unit rely on DMA (Direct Memory Access) to swap the ...
0
votes
1answer
100 views

Calculating cache memory based on LRU algorithm

Assuming i have 4 blocks of cache memory, Using the LRU (Least Recently Used) replacement algorithm on this following sequence of access to memory blocks: 1 2 3 4 5 2 5 4 1 5 2 3 : ...
0
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0answers
33 views

Roles of the Memory Management Unit

I know that the first instruction stored in BIOS is "mapped" to memory address 0, and that a signal on the reset pin to the microprocessor causes this instruction to be fetched, beginning the POST and ...
3
votes
1answer
76 views

Recent Garbage collection survey paper

Many years ago I read a GC survey paper that was updated every few years with advances; I tried to find such a paper today to point a questioner on Stackoverflow at. However all I can find is very ...
0
votes
1answer
77 views

How exactly MOV AX will load data from RAM?

Somewhere on Internet I read : Whenever word size is greater than memory cell size, then there is a need for accessing multiple memory cell Example: for 16 bit processor: MOV AX [2000] To transfer ...
5
votes
1answer
44 views

Can multiple tasks in an RTOS share one stack to save memory?

Many small embedded systems have a limited amount of RAM, 10k or less. I know you can run an RTOS on such systems, however, a realistic number of tasks in such a system is very low, mainly because ...
9
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1answer
42 views

Memory ballooning in the OS

Some hypervisors optimize memory usage using a method that is called ballooning (at least that's what KVM calls it), this method deduplicates memory between VMs and sets common pages to read-only with ...
6
votes
1answer
121 views

Writing a multitasking operating system for a processor without MMU

I've been thinking of writing a hobby operating system for some of the ARM processors. There are many popular single-board computers with ARM MPU, so I simply wanted to purchase one of those (choosing ...
2
votes
1answer
190 views

Practical Page-Replacement Algorithms

Could anyone suggest other page replacement algorithms that are applicable to the real world aside from FIFO, Second Chance (Clock), Enhanced Second Chance and Random?
1
vote
1answer
630 views

What's the difference between Clock and Second Chance Page-Replacement Algorithm?

I know that they both have reference bit, but I only understand the Second Chance but not the Clock Page-Replacement algorithm. could anyone help me understand?
3
votes
1answer
145 views

How, in hardware, MIPS can access a word in the middle of an address

This is am example of a RAM address in the MIPS architecture (32 bits) I can imagine the RAM as having 32 pins just to inform the RAM address I want to access, so I can access each of these words ...
1
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2answers
134 views

How exactly the “load word” instruction loads from RAM?

PS: MIPS architecture This is a model of a memory RAM of 4GB: it has 4,294,967,295 addresses, and each address has 32 bits. Can somebody tell me why the load word instruction needs an offset to the ...
2
votes
1answer
167 views

How does the OS know the physical address of a process' first memory page?

If I have a program, its instructions are stored on the hard drive. When I double-click the executable the pages of memory for this process must get loaded in to RAM. However, for the pages to get ...
6
votes
1answer
96 views

Tag-free garbage collection for object oriented languages

I'm looking around for a good garbage collection technique for my language and found this paper, where Benjamin Goldberg describes a garbage collection technique for strongly typed languages, which ...
0
votes
1answer
59 views

How is heap memory allocated to a process?

I want to better understand how OS provides heap memory to a process. Here by heap memory I mean the memory allocated dynamically, say by call to malloc. When a ...
0
votes
1answer
37 views

In Pagination, how does the S.O. knows where the page is in secondary Memory?

So every process has its own Page Table, the page table references the frame where the page is in physical memory and also has a valid-invalid bit that tells whether it is in physical memory or in ...
3
votes
1answer
70 views

Session Memory in the Windows Kernel

While reading the paper Effective Data-Race Detection for the Kernel by John Erickson and Madanlal Musuvathi. I was stuck on a slightly tricky sentence. "Similarly, a range of kernel-address space, ...
2
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1answer
66 views

Maximum amount of memory that can be allocated to a process

DISCLAIMER: The following scenario was taken from an assignment I got in a OS course I'm taking, and it arose a lot of question marks in my head. However non of the questions asked by myself here ...
2
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2answers
94 views

How to filter a very, very large file

I have a very large unsorted file, 1000GB, of ID pairs ID:ABC123 ID:ABC124 ID:ABC123 ID:ABC124 ID:ABC123 ID:ABA122 ID:ABC124 ID:ABC123 ID:ABC124 ID:ABC126 I would like to filter the file for ...
0
votes
0answers
374 views

Size of memory in 64-bit computer system

I'm new here, a brief intro, I'm a student majoring in comp-sci. Right now I'm having a bit of confusion to answer one of my assignments, it is about system paging. I want to know how am I able to ...
2
votes
3answers
97 views

Does exploiting a spatial Locality in Cache always leads to a lower miss rate?

I've read that, incorporating many words(spatial locality) per cache blocks leads to lower miss rate. Is it the case always? One possibility of such approach is to make a single cache block of size ...
10
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2answers
149 views

Are there any garbage collectors that take into account paging?

Garbage collections have to visit all objects that are alive, so as to find the memory that can be reclaimed. (Having many generations’ just delays this a bit) All things being equal, it is ...
1
vote
1answer
27 views

What memory locations will the CPU fetch instructions from with instruction length of 16bits

While reading Stallings OS Internals and Design, I run into problem. Here is example from the book. For example, consider a simplified computer in which each instruction occupies one 16-bit word ...
1
vote
1answer
40 views

Qubits Related to RAM?

I read in this article that the amount of bits that can be emulated by a certain number of qubits is 2^(number of qubits). This is because each qubit can be in one of 2 states after it collapses, and ...
2
votes
2answers
113 views

Which part of the computer allocates memory in RAM?

When we declare a variable there will be a random part of memory will be allocated in RAM. Which component will allocate the memory? Is the processor or any other specific hardware doing the ...
-1
votes
1answer
331 views

Instruction Set Architecture (ISA) design

Yes, this is a homework question, I've tried working it out and was hoping I could get pointed in the right direction. Here's the question: You are designing the instruction set for a new type of ...
2
votes
1answer
2k views

Word- or byte-addressable? Correct terminology

Seemingly, a byte has established itself to be 8bit (is that correct?). RAM and NOR-flash can be normally accessed on a quite granular level, but it is up to the system architecture to determine if ...
-1
votes
1answer
174 views

Does virtual address space resides in virtual memory?

I have several confusion like : Does virtual address space resides in virtual memory ? Does each process has its own virtual address space like each process has its own virtual memory and own page ...
-1
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1answer
85 views
0
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1answer
414 views

Size of address registers and data registers in relation with memory size

Suppose that a processor can address directly up to 4 Gigabyte main memory and can operate words with size 32 bit. Find how big should be the size of the "MAR" (memory address registers), "MDR" ...
0
votes
0answers
1k views

What determines a hit/miss with cache memory?

I was taught that when a reference is mapped to a cache block, X, for the first time, the word is stored in the cache block, bearing a tag and index that helps identify it for future reads. Then, ...
2
votes
2answers
569 views

What is “memory coalescing”?

I came to know that the graphic processing unit have something called memory coalescing. On reading on it I was not clear on the topic. Is this any way related to Memory Level Parallelism. I have ...
-1
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1answer
96 views

processes response time confusion

An OS contains 10 identical processes that were initiated at the same time.Each process contains 15 identical requests. Each request consume 20 msec of CPU time.A request is followed by an I/O ...