Timeline for Finding cache block transfer time in a 3 level memory system
Current License: CC BY-SA 3.0
9 events
| when toggle format | what | by | license | comment | |
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| Apr 14, 2013 at 16:24 | comment | added | Raphael | @avi See my first comment. For more detail, I suggest you ask a computer engineer. As I said, there is no conceptual reason against building a CPU that acts as you say. | |
| Apr 14, 2013 at 16:20 | comment | added | avi | ^Thanks again :) So we have to consider request of lowest level memory. But I have this new doubt, we move only 4 words from main memory to cache L2, so 3/4th of space is not used in a block of cache. Why not move whole 16 words to exploit spatial locality ? Or is it because to save time ? | |
| Apr 14, 2013 at 15:57 | comment | added | Raphael | @avi I think my answer covers this already. :) (Glad I could help. I use cautious phrasing because one could very well build a processor for either option; insofar, the question is ill-posed, asking for best-practice as opposed to scientific fact.) | |
| Apr 14, 2013 at 15:01 | comment | added | avi | But what about miss in L2 ? Now requesting source is L2, so we have to move 16 words from main memory Or we have to consider the request of lowest level memory, L1 ? In that case it will be (2+20+200)ns. If not, if we have to move 16 words from main memory to L2, then it will be 2+20+(200*4) = 822ns, which is not in option. | |
| Apr 14, 2013 at 14:45 | vote | accept | avi | ||
| Apr 14, 2013 at 14:45 | comment | added | avi | I think you can remove words 'as far I know', I just thought for a moment & checked & you are absolutely right. I have prepared my notes from various credible sources & I have mentioned it. Somehow I forgot it while solving this. The size is always decided by source. So, for question 1, it will be (20+2) ns, even though we are moving only 4 words. | |
| Apr 14, 2013 at 13:34 | comment | added | Raphael | @avi As far as I know, yes. Why would you load more? Right now, we even only need one out of these four. Even if data locality is maintained, it's arguably better to spread the latency out over more statements, as it yields a more predictable performance profile and isolated accesses are not punished that much. | |
| Apr 14, 2013 at 12:44 | comment | added | avi | I did not get you. So only 4 words (L1 cache size) will be transferred from L2 to L1 ? | |
| Apr 14, 2013 at 11:45 | history | answered | Raphael | CC BY-SA 3.0 |