Timeline for How to know the width/size of a IR (Instruction Register)
Current License: CC BY-SA 4.0
6 events
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| Dec 7, 2020 at 12:31 | comment | added | Karl M | I have found one example I want to show you see: ww1.microchip.com/downloads/en/devicedoc/… on page 19, 2.11 Direct Programming Addressing, JMP and CALL. It shows that it splits it in parts: first part OP, second part 6 MSB. And the second cycle it fetches 16 LSB. After that it executes the instruction and puts the data into the PC. | |
| Dec 7, 2020 at 12:21 | comment | added | Karl M | I understand that the most interesting part is decoding the IR. That is the part where it makes sense for the CPU what to do with the instruction. What I understand from your comment is that CALL is a 2-word instruction. The first word is the instruction and the second word is pure data. So, does this mean that it takes one more cycle? Because, first it decodes the instruction than it sees that it needs an operand. It fetches the operand (pure data) into the IR and then it can execute the instruction? Am I correct? I appreciate the help you are offering. | |
| Dec 7, 2020 at 12:11 | comment | added | Pseudonym♦ | The interesting part is the decode logic which takes up most of the left-hand side of the diagram. Ignore the predecode register and predecode logic; that is only there for pipelining and interrupt handling. The ultimate result of instruction decoding is the few dozen single-bit control lines coming out of "random control logic". This (as well as the "decode ROM", which is actually a PLA) is combinational logic whose inputs are the IR and various timing/control flip-flops. This is much easier to generate from the IR than from reduced set of opcodes. | |
| Dec 7, 2020 at 12:01 | comment | added | Pseudonym♦ | So let's take a two-word instruction such as CALL as our example. The second word of that instruction is pure data. So the control signals within the CPU core can be generated entirely from the first word, which can be held in the IR until the instruction has completed. It doesn't make a lot of sense to compress all 16 bits of the instruction word into an 8-bit opcode only to decompress it into individual control signals again later. It might help to look at a more detailed diagram, such as the famous 6502 block diagram from this paper: projects.ncsu.edu/wcae//WCAE1/hanson.pdf | |
| Dec 7, 2020 at 10:23 | comment | added | Karl M | I am a little confused, and I hope you can clarify it. The AVR example that you have mentioned has around 131 instructions. I have checked it in the datasheet and on the first page it is mentioned: "131 Powerful Instructions – Most Single Clock Cycle Execution". 131 instructions can fit easily into 8-bits, because 2^8=256 (and 2^7=128 too less) so 8-bits instruction. What I don't understand is that some of these instructions need a memory address to hold as an operand. How do the CPU handle this? Because the IR size is 16-bits but it only has 8-bits instructions. Thank you. | |
| Dec 6, 2020 at 23:20 | history | answered | Pseudonym♦ | CC BY-SA 4.0 |