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When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, LDA instruction (load address from memory, load word from that address. )

Illustrated in timing diagram below.

How is this usually solved (could be different across different CPUs but there are probably trends. )

Is a temporary register used (the "memory address register" could load and output in two separate steps), or is the timing issue just not a problem and tends to work out regardless?

Example LDA with two step "memory address register",

      when LDA_1 =>           -- Load accumulator from operand
        addr_in <= dr;
        
        state := LDA_2;
      when LDA_2 =>
        addr_out <= addr_in;
        
        state := LDA_3;
      when LDA_3 =>
        pc <= pc + one;
        addr_out <= pc + one;
        
        state := load_opcode;

When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, LDA instruction (load address from memory, load word from that address. )

Illustrated in timing diagram below.

How is this usually solved (could be different across different CPUs but there are probably trends. )

Is a temporary register used (the "memory address register" could load and output in two separate steps), or is the timing issue just not a problem and tends to work out regardless?

Example LDA with two step "memory address register",

      when LDA_1 =>           -- Load accumulator from operand
        addr_in <= dr;
        
        state := LDA_2;
      when LDA_2 =>
        addr_out <= addr_in;
        
        state := LDA_3;
      when LDA_3 =>
        accu <= dr;
        
        state := load_opcode;

Timing with temporary "address in" register illustrated below,

When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, LDA instruction (load address from memory, load word from that address. ) How is this usually solved (could be different across different CPUs but there are probably trends. ) Is the memory address register a "two state" register that loads the address on one clock cycle, and outputs the new one on the next, or does the timing tend to work out regardless?

Illustrated in timing diagram below.

When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, LDA instruction (load address from memory, load word from that address. )

Illustrated in timing diagram below.

How is this usually solved (could be different across different CPUs but there are probably trends. ) 

Is a temporary register used (the "memory address register" could load and output in two separate steps), or is the timing issue just not a problem and tends to work out regardless?

Example LDA with two step "memory address register",

      when LDA_1 =>           -- Load accumulator from operand
        addr_in <= dr;
        
        state := LDA_2;
      when LDA_2 =>
        addr_out <= addr_in;
        
        state := LDA_3;
      when LDA_3 =>
        pc <= pc + one;
        addr_out <= pc + one;
        
        state := load_opcode;

When an operand encodes an address, such as in a Load accumulator (LDA) instruction, it seems like a temporary address storage register is needed. Otherwise, reading the address into standard address register should result in the addressed memory changing while reading the word at the address.

Illustrated in timing diagram below.

How is this usually solved (could be different across different CPUs but there are probably trends. ) Is it a temporary register, or does the timing tend to work out regardless?

When an operand encodes an address, and that address changes the "memory address register" and the word in memory being addressed, it seems like timing issues could be a problem. Examples, LDA instruction (load address from memory, load word from that address. ) How is this usually solved (could be different across different CPUs but there are probably trends. ) Is the memory address register a "two state" register that loads the address on one clock cycle, and outputs the new one on the next, or does the timing tend to work out regardless?

Illustrated in timing diagram below.