Timeline for Finding cache block transfer time in a 3 level memory system
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| S Oct 30, 2014 at 0:24 | history | suggested | CommunityBot | CC BY-SA 3.0 |
corrected answer
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| Oct 29, 2014 at 18:16 | comment | added | Arjun Suresh | I'm sorry- I got that wrong. I have corrected the answer as 22ns and 902 ns. But the bandwidth is 4 words only as shown in the diagram on question. | |
| Oct 29, 2014 at 18:14 | review | Suggested edits | |||
| S Oct 30, 2014 at 0:24 | |||||
| Jun 19, 2014 at 19:49 | comment | added | Wandering Logic | I don't think this is correct. See the comments under the accepted answer. Nowhere does it say that the "data bandwidth is 4 words". | |
| S Jun 19, 2014 at 12:46 | review | Late answers | |||
| Jun 19, 2014 at 20:15 | |||||
| S Jun 19, 2014 at 12:46 | review | First posts | |||
| Jun 19, 2014 at 13:11 | |||||
| Jun 19, 2014 at 12:27 | history | answered | Arjun Suresh | CC BY-SA 3.0 |