Timeline for How on-chip multithreading prevents cache misses from stalling a processor pipeline?
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
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| Oct 28, 2018 at 17:44 | comment | added | gnasher729 | @HumbertoFioravanteFerro A processor with hyperthreading absolutely relies on OOO execution capabilities - it just uses them to execute instructions from another thread even when the first thread has dispatched its operations earlier. | |
| Jan 9, 2017 at 12:46 | comment | added | Humberto Fioravante Ferro | Although a bit obvious, it is important to emphasize that SMT makes out-of-order execution somewhat redundant (and therefore inefficient). In an article entitled "Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading" (web.eecs.umich.edu/~twenisch/papers/isca16.pdf), the authors exploit this subject and conclude that "Whereas OOO execution can improve performance for moderately threaded SMT designs, the resulting hardware utilization is inefficient, as many instructions are scheduled in-sequence". | |
| Jan 8, 2017 at 21:47 | vote | accept | Humberto Fioravante Ferro | ||
| Jan 8, 2017 at 21:46 | comment | added | Humberto Fioravante Ferro | This is new for me: so far, I thought that only superscalar pipelines could deal with different instructions at the same processing stage in the same clock cycle. And it was precisely this notion that was driving me crazy: I wondered how an instruction could "sleep" while new instructions are being fetched, it made no sense to me. Thank you for clarifying this issue, Gnasher! | |
| Jan 8, 2017 at 13:34 | comment | added | gnasher729 | As an example, the AMD Zen architecture can handle 72 simultaneous out-of-order loads. "Can't have two instructions at the same stage of the pipeline"? A modern processor laughs at that. Try 150 instructions that can wait for dependencies. | |
| Jan 7, 2017 at 16:57 | comment | added | Humberto Fioravante Ferro | I thought about that: out-of-order execution annihilates data dependencies between subsequent instructions and therefore no cycle is wasted (no stall in the pipeline). That's crystal clear to me. The problem is when Tannenbaum states that independent instructions (from different threads) can be processed by a pipeline stage that is currently processing a cache miss. That's another story. It won't help to change the order of execution (or process another thread) if a instruction has to wait for the main memory because you can't have two instructions at the same stage of the pipeline. Right? | |
| Jan 7, 2017 at 13:20 | history | answered | gnasher729 | CC BY-SA 3.0 |