Skip to main content
edited title
Link
xskxzr
  • 7.6k
  • 5
  • 23
  • 47

Every circuit of size at most $S$ can be representd as a string of $9S \log Sbits$S$ bits

Source Link
theQman
  • 597
  • 3
  • 8

Every circuit of size at most $S$ can be representd as a string of $9S \log Sbits$ bits

I'm trying to understand this claim. I see that if there are $S$ vertices, then we can identify each vertex using $\log S$ bits. Now each vertex can be connected to, let's say, $S$ other ones (is there some sort of restriction to the fan-out that I'm unaware of?). If we use an adjacency list, then for each vertex, we wold need to store up to $S \log S$ bits. Doesn't this lead to $S^2 \log S$ bits, since we need a list for each vertex? And where does the $9$ come from?