Memory Address Lines

Question

I am reading a text book by David Tarnoff and there is something I do not understand, the section is on CPU and memory. The book states that the number of address lines going into a memory device determines the number of addresses which makes sense to me, as it says for $n$ address lines going into the device there will be $2^n$ addresses.

What doesn't make sense is this:

a memory device with 28 address lines going into it has $2^{28}$ = 256 Meg locations. This means that 28 address bits from the full address must be used to identify a memory location within that device. All of the remaining bits of the full address will be used to enable or disable the device.

I do get the concept of the full address but I do not understand how if there are only 28 address lines and each carries one bit, and its a 28 bit address how there can be any more data because there are no more address lines to carry the bits used to enable or disable the device?

In the previous chapter the books also talks about a chip select being used to activate a memory device, but now says that part of the full address is used for this All of the remaining bits of the full address will be used to enable or disable the device.

Could somebody help me understand this please?

Answer 1

if there are only 28 address lines and each carries one bit how there can be any more data?
I don't read 28 address lines all told, but 28 address lines going into one specific memory device.

where are the 4 address lines to carry [the 4 bits out of 32 that are used to activate the memory device]?
There are two answers on the conceptual level:

• A> Those are the most significant bits
• 1> As long as the "gaps" in the address space that are not handled by the device when not addressed by contiguous least significant bits are handled properly, it doesn't matter.
  For details on why and how this may be done purposefully, read up on memory controllers and interleaved memory.