RAM architecture vs. CPU architecture

Question

I have learned that initially PCs had 8-bit memory architecture and that 1 byte (i.e. 8 bits) was the "basic" memory unit because 8 bits was exactly the memory space required to encode any of the original ASCII 128 characters ($2^7=128$, with the last 8th bit used for parity checking).

My understanding of this is that the 8-bit RAM architecture meant that every byte had a unique memory address (so it was possible to uniquely address each byte, but it was not possible to address the bits inside the bytes).

My understanding is that when we code in something like C or C++, the pointers point to the address in the RAM (so in the 8-bit architecture, we could point to any one Byte in the memory).

Now, how does the CPU architecture come into the picture? I understand that the CPU bit-width determines the maximum number of bits that the CPU is able to process in "one chunk": but does this need to exactly correspond to the bit-width of the RAM?

We now live in a 64-bit "architecture" era. My understanding is that this refers to the CPUs (not the RAMs).

My questions:

• Could a 64-bit CPU work with 32-bit RAM? (and how would this work? Please give an example)

• When we have a 32-bit RAM (or a 64-bit RAM), does it mean that each memory address points to a 32-bit (or a 64-bit) wide memory location, and we cannot point to any lesser-wide part of the memory?

• Could a 32-bit processor work with a 64-bit RAM (and how would this work?)

Answer 1

Computers have had a number of different ways of managing mismatches between bit count and memory size over the years. The general theme is that "pure" n-bit CPUs are rare. Instead, CPUs use a mix of sizes for different purposes.

Most early computers were word-based, with 36-bit words being popular. The minimum addressable unit was one word: the processor would load, operate on, and store data in word-sized chunks. These had the potential to address a lot of memory (68,719,476,736 words for a 36-bit machine), but as a money-saving measure, most of the potential address lines were omitted. This omission of address lines has been a frequent way of simplifying designs over the years: the computer you're using right now is probably 64-bit, but only has 52 of the address lines actually wired up.

The Intel 4004 and some other CPUs use a multiplexed bus, where addresses and data travel across the same set of lines. In the case of the 4004, it's a 4-bit CPU with 12-bit addressing. Reading or writing to RAM involves emitting three four-bit address fragments which are picked up by an external circuit to select a memory cell, then reading or writing that cell.

Most early 8-bit CPUs, such as the the MOS 6502, use 16-bit addressing. They have 8 data lines and 16 address lines. Internally, the CPU either has dedicated 16-bit address registers or can combine pairs of 8-bit registers to produce a 16-bit memory address. Such a CPU might write to half an address register at a time, or it might have dedicated 16-bit address-generation circuitry.

The Intel 8086 and descendants use memory segmentation to let a 16-bit CPU access a million addresses. The CPU stores addresses in a 16-bit "segment register" and a 16-bit "offset register", and a special circuit in the CPU merges them to produce a 20-bit memory address. The purpose of this is to let a purely 16-bit program run on the CPU: the OS sets up the segment registers, and the program can then treat the computer as having 64k of RAM. This segmentation technique has resurfaced at least twice: with PAE on the Pentium Pro and later to let a 32-bit CPU access more than 4 gigabytes of RAM, and then with 32-bit mode on x86-64 CPUs to let 32-bit programs run on 64-bit systems.

And this is all without getting into the complexity of things like Harvard architectures (where instructions and data are stored in separate memories, with potentially different bit counts), parity RAM (where one additional bit is stored per minimum addressable unit, such as using nine bits to store an 8-bit byte), and error correction, (where memory is grouped into "error domains" and additional bits are used to spot and correct errors).