Modern personal computers as far as I understand have increased in power (measured informally by ability to compute “more demanding programs”) due to two “broad factors”:

  • decreased transistor size (thereby decreasing delay time between computations).

  • increased transistor quantity

It seems to me that the first factor should speed up any existing design (it simply allows a higher frequency of computations without a change in design), but it seems to me that the second factor generally requires a change in design in order to actually improve performance.

So I am trying to understand how increasing the number of transistors in a CPU can help you increase computations. I’ve looked online but couldn’t find a definitive answer.

My current understanding is that in order to leverage an increase in transistors to get increased performance, you need to employ various kinds of parallelism.

  • By increasing the word size of CPU’s from 1 bit to 2 bit to 64 bit, modern CPU’s can use bit-level parallelism to perform more computations in a single instruction.

  • By employing smart control architectures (i.e. in the control unit), a CPU can smartly handle multiple instructions that don’t require the same CPU components at the same time, thereby employing instruction-level parallelism

  • By splitting instructions into parts, a CPU can get parallelism through pipelining, by performing the first parts of instruction B before the last parts of instruction A are done.

These are various ways in which we can use more transistors to get more performance, and they all use the increased number of transistors in some way to perform the same computations that earlier computers did, but now they do it in parallel.

Is my understanding correct, that the primary/only channel through which increased transistor count results in increased performance is through parallelism? Or are there ways that we can use increased transistor count to improve performance that rely on other techniques than parallelism?


1 Answer 1


There are at least 3 architectural tricks by which an increased number of transistors can lead to higher performance.

One of them is parallelism, as you point out.

A second technique trading off more transistors for performance is speculation. Often speculative execution of some kind is combined with parallelism, and this kind of performance optimization happens at all levels. For example: A carry-select adder compputes both a+b+0 and a+b+1 and then selects the correct answer when the carry bit becomes available. In predicated execution we might execute instructions before we know their results are needed, and then commit the results to the register file only once we know the computation was needed. In checkpoint repair we speculatively execute instructions that follow an instruction that might (but probably won't) cause an interrupt. And similar approaches can be used to speculatively execute the instructions that follow a branch instruction. Prefetching uses extra transistors to fetch data or instructions that might (but won't necessarily) be needed in the future.

Both branch speculation and prefetching are often augmented with even more transistors to predict what intructions/data has the highest probability of being useful in the future.

A third approach for trading off transistors for performance is caching. A cache is a (usually small and fast) memory used to store the results of expensive work, so that if an identical request is made in the future the result can be returned from the cache rather than by recomputing the result.

  • $\begingroup$ Speculation appears to be tightly bound to parallelism. E.g., rather than just waiting for the condition of a branch to resolve, execute one path in parallel with waiting. Strength reductions besides localized storage (caching implies non-software management, excluding registers and scratchpad): result forwarding (rather than waiting until after register writeback), integration (reducing communication costs), decode caching, and recent register renaming tricks (move elimination, zeroing optimization). (Spatial locality is parallelism/speculation, temporal locality is strength reduction.) $\endgroup$
    – user4577
    Commented Nov 27, 2018 at 13:48
  • $\begingroup$ Software optimization can also be facilitated by (or depend upon) aspects related to increasing per chip transistor count. Compiler or programmer CSE can depend on faster localized storage; instruction scheduling is less useful in non-pipelined designs (the drum scheduling in "[The Story of Mel](www.catb.org/jargon/html/story-of-mel.html)" is one exception). $\endgroup$
    – user4577
    Commented Nov 27, 2018 at 13:49

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