# Architecture - calculating miss penalty

I know that AVG Memory Access Time = Hit time + Miss Rate * Miss Penalty

If I am given the AMAT and miss rate, aswell as the latency to access memory(call this x) how do I calculate the miss penalty & / or Hit Time?

For example:

AMAT = 80 (cycles)
Miss Rate = 0.4
Memory access latency = 60 (cycles)


How do I get miss penalty from this so that I can solve for hit time?

Thanks

• Can you provide a url or reference to the original source of the problem? It is rather pointless if we are dealing with a low-quality source. Even reputable sources can have typos, lapses and even glaring errors. The more context, the faster the situation can be cleared. Nov 28 '18 at 17:35

Let us assume/understand that "memory access latency" means the "memory access latency" to access the cache when there is a hit. (It appears reasonable to just say "memory access latency" since the latency to access the cache might be (almost) the same whether there is hit or miss.) Otherwise, there is no solution to this problem or we have to introduce other less straightforward assumptions.

Once we have made that assumption/understanding, the miss penalty is easy to solve.

Miss Penalty = (AMAT - Hit time) / Miss Rate
= (AMAT - hit-rate * memory-access-latency) / Miss Rate
= (80 - (1 - 0.4) * 60 ) / 0.4
= 110


However, it is rather unnatural to interpret "memory access latency" as referring to accessing the cache since by default, "memory" refers to the main memory while the cache memory, L1 memory and L2 memory are referred as cache.

Another plausible situation is the last given condition is, for example, memory access latency = 160 instead of memory access latency = 60. Then we can understand "memory access latency" as, very naturally, the latency to access the main memory when there is a cache miss. I put an emphasis because it is reasonable to assume there is no way to skip the cache (in this kind of exercises). Note that this natural interpretation cannot make much sense originally when the value is 60, which is less than the given "AVG Memory Access Time", 80. I will leave the question as an exercise for you if the last condition is indeed changed to memory access latency when there is miss = 160.

(Yet another way to resolve the situation is to change AVG Memory Access Time = 80 to, for example, AVG Memory Access Time = 30.)

You may check my answer for related information.

• thanks. Another answer I received stated: "When there is a single cache level, the memory access latency is the same as the cache miss penalty, which seems to be the case here. So the miss penalty is 60 cycles. Now you can substitute these values in the formula and calculate the hit time." Im assuming this is incorrect? Nov 28 '18 at 9:48
• "The memory access latency is the same as the cache miss penalty". This is one of the contorted assumptions. The design of the cache is to shorten the time to serve an access to memory. "When an attempt to read or write data from the cache is unsuccessful, it results in lower level or main memory access and results in a longer latency and this phenomenon is known as a cache miss", says Wikipedia. The cache miss penalty means the extra time needed compared to when the cache is not missed. Nov 28 '18 at 17:21
• so in the example, the latency to access memory should be greater than the AMAT, so that the answer above makes sense? Nov 28 '18 at 19:42