In pipelining (at least, in MIPS), why is the incremented program counter address saved in the IF/ID pipeline register?

Question

In D. Paterson's book, Computer Organization and Design, Fifth Edition, there is a paragraph that says

Instruction fetch: The top portion of Figure 4.36 shows the instruction being read from memory using the address in the PC and then being placed in the IF/ID pipeline register. The PC address is incremented by 4 and then written back into the PC to be ready for the next clock cycle. This incremented address is also saved in the IF/ID pipeline register in case it is needed later for an instruction, such as beq. The computer cannot know which type of instruction is being fetched, so it must prepare for any instruction, passing potentially needed information down the pipeline.

I'm trying to understand why an incremented address must be saved in the IF/ID pipeline register, at least in MIPS. I understand that it might be needed by some instruction somewhere later.

However, how does an instruction such as beq use the program counter value?

Answer 1

beq doesn't contain the destination address in the instruction, but an offset relative to the location of the instruction. For example "branch if equal to the instruction 12 words ahead of the branch instruction". You cannot execute such an instruction if you don't know what the address of the branch instruction was.