I understand how the control, data and instruction buses form the system bus in von Neumann architecture but in the context of Harvard architecture, my textbook refers to "parallel data and instruction buses". The Wikipedia article for Harvard architecture also refers to an instruction bus: "TMS320 C55x processors, for one example, feature multiple parallel data buses (two write, three read) and one instruction bus."

What is an instruction bus? Based on its name, I'd guess it allows the processor to send instructions to components but in that case, how does it differ from a control bus?


1 Answer 1


I believe you have one bus too many. Taking the image from teach-ict.com:

Von Neumann architecture

The diagram shows two buses with memory and one internal bus. One memory bus fetches instructions (stored in memory) to the Control Unit and data (stored in the same memory) to the ALU. The second bus is the Address Bus which says which memory to read or write (both for instructinos and data).

The Control Unit decodes the instruction and tells the ALU what to do (add, subtract, divide...). The Control Unit and the ALU together are called the CPU.

There is no separate Control Bus with the memory. The Control "Bus" is internal in the CPU.

Harvard Architecture

In the Harvard Architecture there is physically separate memory for instructions and data. It means there are 4 buses, 2 data buses (1 for instructions and 1 for data) and two address buses (1 to address the instruction memory and 1 to address the data memory). The "Control Unit" in the diagram is the combined Control Unit and ALU from the previous diagram, the CPU. Any Conrol "Bus" is internal to that unit.

To summarize the answer: a Control Bus is internal to the CPU and should not be considered in discussing interactions with memory. There is no Control Bus with memory.

(Note: The Input and Output shown in the Von Neumann diagram should be ignored, or should be considered also present in the Harvard Architecture.)

  • $\begingroup$ Thanks for your response. I'm a bit puzzled about how the control bus is internal to the CPU when Wikipedia refers to communication between the CPU and "other devices". There are also a large number of diagrams showing connections from memory to the control bus, including this one and this one. My textbook also explicitly discusses interactions between the CPU and memory over the control bus. $\endgroup$
    – LJD200
    Dec 9, 2018 at 17:44
  • $\begingroup$ You can see the "control bus" as all the additional signals from the CPU to other devices, such as IO, IRQ and DMA signals. But a "bus" is typically characterised by a width and carrying all the same signals. The address bus has address bits, the data bus has data bits, but the "Control Bus" does not have a width. That is why I do not see it as a bus (but rather a collection of "other" signals). $\endgroup$ Dec 9, 2018 at 17:50
  • $\begingroup$ The "control bus" is typically a result of the system design. Data and address busses are not (except for their width). $\endgroup$ Dec 9, 2018 at 17:54

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