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There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on the concept of value locality.

What I wonder if there is any commercial CPU from Intel/AMD/ARM that actually uses any of these techniques, or are they still far away from being implemented in CPUs?

I mostly see these techniques as the runtime, CPU version of compiler optimizations such as common-subexpression elimination, loop invariant code motion, redundant load removal, catching cases that cannot be handled due to pointer aliasing, side-effects, etc.

Two of the papers that seem to have introduced these ideas:
Dynamic instruction reuse
Value Locality and Load Value Prediction

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    $\begingroup$ Could you reference some important/influential/popular papers among "a lot of research"? That should help readers learn and understand. $\endgroup$
    – John L.
    Dec 23, 2018 at 13:30
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    $\begingroup$ Added links to the two papers that seem to have proposed these approaches, each with >400 citations. $\endgroup$
    – Gratian Lup
    Dec 23, 2018 at 19:15

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Modern Intel processors use prediction of values in several situations.

One, when the target of a branch instruction is stored in memory including the location where the return address of a call is stored, that value is predicted.

Second, when a store is followed by a load, it is predicted whether the addresses are the same (or overlapping) or not. That allows the load to be performed speculatively even before the value to be stored is calculated, if it is predicted that the addresses are different.

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    $\begingroup$ These are not the kind of value predictions the poster has in mind; see the papers referenced in the question. $\endgroup$
    – user4577
    Dec 24, 2018 at 11:07
  • $\begingroup$ Well, it's the kind of value predictions that actually happen. $\endgroup$
    – gnasher729
    Dec 24, 2018 at 21:31
  • $\begingroup$ OK, I think it's safe to assume that no CPU currently uses these techniques. It makes sense, Intel/AMD would likely have mentioned they've got some new advanced technique... With neuronal (perceptron) branch prediction it took almost 20 years from the first paper to having an actual architecture using it (Zen). $\endgroup$
    – Gratian Lup
    Dec 25, 2018 at 2:09
  • $\begingroup$ @GratianLup afaik, Zen was first to use this fact for asvertizing but the tehcnlogy itself is widely used in industry. I have seen it mentioned in Samsung M3 core f.e., and I can't believe that AMD and Samsung are ahead of Apple/Intel $\endgroup$
    – Bulat
    May 23, 2019 at 18:17

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