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I found the following question -
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero
If the clock (Clk) frequency is 1GHz, then the counter behaves as a
(A) mod-5 counter
(B) mod-6 counter
(C) mod-7 counter
(D) mod-8 counter
What I can see is, in this particular case clock time period is smaller than the delay in the NAND gate. But I am unable to see how it will affect the counter exactly!
ANS: MOD8 COUNTER
It still is a mod 8 counter only. But the point where anyone can get confused is the clock speed and the nand gate delay. Basically as soon as we get 111 as the answer. the nand gate gets set to 0 and hence the reset is activated now one may argue that because of this the counter won't count further as it already has the reset pin on. However since the delay of nand gate is more than the time required for the counter to give next output thus before the nand gate could change the counter to 000. The counter would have already produced the next sequence that is 001. that would help it get out of the reset configuration. Steps can be written as follow:-
counter produces 111
nand gate receives 111 and starts processing it
counter produces 000
nand computes 0 and hence counter is set to reset i.e. 000.
nand receives 000, processes it and the counter gets out from reset state.
counter produces 001 as expected.
The only change one could observe with this configuration compared to the normal 3 bit counter is the duration for which the counter would produce the state 000. Rest all would remain the same. Let me know if I could help you further.
