I found the following question -
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the counter is assumed to be zero
If the clock (Clk) frequency is 1GHz, then the counter behaves as a
(A) mod-5 counter
(B) mod-6 counter
(C) mod-7 counter
(D) mod-8 counter
What I can see is, in this particular case clock time period is smaller than the delay in the NAND gate. But I am unable to see how it will affect the counter exactly!