# Handling of $HALT$ instruction

I have been reading $$CO$$ by Carl Hamacher. I have read generally $$PC$$ is incremented during the fetching phase of the instruction only, so if interrupt occurs because of branching or call during execution of instruction, then first the current instruction is completed followed by the storage of address of next instruction (or simply, storage of current $$PC$$ value).

But I have got some doubts concerning $$HALT$$ instruction. Suppose there is a 4 byte $$HALT$$ instruction at memory location $$1000$$. Then

• What will be the $$PC$$ value and return address saved on stack if interrupt occurs during execution of $$HALT$$? $$1004$$ or $$1000$$?
• I have read $$HALT$$ instruction is actually uncondition branch instruction on itself. Is it true? Any reference for this statement?
• Is this particularly tied to an architecture? – b degnan Jan 8 at 15:22
• No @bdegnan I was looking for a generalized answer . – Mr. Sigma. Jan 11 at 2:22