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I am reading William Stallings Computer Organization & Architecture to understand about control unit & micro-operations.

Stallings explain that interrupt cycle requires 3 time units to complete :

t1 : MBR <- (PC)
t2 : MAR <- Save_Address
     PC <- Routine_Address
t3 : Memory <- (MBR) 

t1 : Save the current PC value to MBR

t2 : Save_Address provides the memory location where the value of PC has to be stored. It is saved in MAR.

Routine_Address gives the address for Interrupt Service Routine

t3 : The MBR (which has old value of PC) is stored to memory location (whose address provided by MAR)

But this is how I am thinking, the above operations can be completed in only 2 time units.

t1 : MBR <- (PC)
     MAR <- Save_Address
t2 : PC <- Routine_Address
     Memory <- (MBR) 

I checked twice & I find no dependency among micro-operations performed in time unit t1 & t2.

So, is my approach correct ?

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Your approach will work. There are no hard and fast rules in micro-op scheduling. The number of micro-ops that can be executed in parallel depends on the internal organization of the CPU. Clearly, we cannot reload the program counter (PC) until we save its contents, but there is nothing stopping us from saving its contents on the leading of the clock signal and loading new contents on the trailing edge.

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Maybe the transfers in t1 and t2 share some component in the datapath, such as a bus for making the transfer. Where does Save_address come from?

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