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To be precise I am here for RAW hazard. Consider a 5 stage pipeline . enter image description here

In case of $I_4-I_1$ dependency , I am not sure if it is an $RAW$ hazard as $I_4$ does not depends on value of $R_1$ that $I_1$ gives. and even if it fetches it ,it still be a wrong value as per the instruction sequence as $I_2$ is modifying it.

So , is $I_4-I_1$ a $RAW$ hazard ?
and if yes, then please give suitable explanation why so and related information about $RAW$ hazard as it happened even if $I_2$ modified the Value in between .

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    $\begingroup$ We can't say without knowing number of stages used in pipeline. If stages are not more than 3, it's not RAW $\endgroup$ – Mr. Sigma. Dec 31 '18 at 12:50
  • $\begingroup$ In 5 stage pipeline ? ( edited ) $\endgroup$ – CHETAN RAJPUT Dec 31 '18 at 13:05
  • $\begingroup$ What my concern is , R1 is modified by I2 then why still I4-I2 on R1 is a hazard ? $\endgroup$ – CHETAN RAJPUT Dec 31 '18 at 13:07
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We can't say without knowing number of stages used in pipeline. If stages are not more than $3$, it's not RAW.

First of all, this statement of mine is incorrect if we talk about data dependency. Dependency is a matter of instructions itself, architecture doesn't come into play directly. Architecture can only ensure that stall not to happens even with dependencies but it doesn't change the fact of dependencies among instructions. But in a pipeline if any data dependency results into stall then it is called data hazard.

and even if it fetches it ,it still be a wrong value as per the instruction sequence as I2 is modifying it.

Again, as I have explained above, the modification is irrelevant here if we are just talking about dependencies. To check data hazard What we need to do is to see whether dependencies result into stall in pipelining or not. If yes, it results, then it is data hazard.

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