# Relating L1 cache, TLB and main memory

Earlier while solving problems from computer organization book by Stallings, I came across the fact that

$$T_a=(H_{L1})(T_{C1})+(1-H_{L1})(T_{C1}+T_M)$$
where,
$$T_a \rightarrow$$ Average access time
$$H_{L1}\rightarrow$$ L1 cache hit ratio
$$T_{C1}\rightarrow$$ Time to access L1 cache
$$T_{M}\rightarrow$$ Time to access memory

Now while solving problems from Operating systems book by Stallings, I came to know

When main memory contains page table and some of its entres are contianed in translation lookaside buffer (TLB), then
Effective access time $$=H_{TLB}\times\left(\underbrace{T_{TLB}}_{hit}+\underbrace{T_{M}}_{ \begin{matrix} accessing \\ actual \\ page \end{matrix} } \right) + (1-H_{TLB})\times\left(\underbrace{T_{TLB}}_{miss}+\underbrace{T_{M}}_{ \begin{matrix} accessing \\ page \\ table \end{matrix} }+\underbrace{T_{M}}_{ \begin{matrix} accessing \\ actual \\ page \end{matrix} } \right)$$

Looking at two different caches L1 and TLB, I get following doubts:

1. Are these two same functionally? (that is does term L1 is used to refer cache storing data while TLB to cache containing page table)
2. Are these two same physically? That is where do they exist? Is TLB maintained in L1 cache only? Or These two are physically separate cache?
3. How these are accessed in order? I feel first L1 is accessed to obtain the page directly. (Then (on L1 miss) possibly any other level of cache L2, L3 etc.) Then (on Lx miss) TLB to fetch the address of the target page. Then (on TLB miss) memory is accessed to fetch the address of the target page from page table. Finally memory is accessed to obtain the page from the address.
4. Does TLB also follows L1 / L2 / L3 cache mapping patterns (direct, fully associative or set associative)?