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5 stage pipline

addi $t1,$zero,0x30 
lw $t2,0($t1)  
sw $t2,0xff18($zero)  
addi $t2,$zero,100

Question is to find hazards existing in the code and the answer is:

  • Hazard 1: Between lines 1 and 2. Register t1. Solved using forwarding.
  • Hazard 2: Between lines 2 and 3. Register t2. Solved using forwarding.

But I found the answer is rather strange,

  • So there is a hazard between line 1 and 2, in the first line t1 writes back in the fifth stage, and in the second line t1 uses in the decode stage, in my opinion there should be a stalling first and then forward to have access to t1 in the second line.
  • I don't see a hazard between line 2 and 3? line 2 t2 write back in the fifth stage, and line 3 fetches t2 in the first stage

Am I thinking something strange, why the correct answer seems not correct to me?

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THe answers are correct. There is a data hazard when the information stored in the "regular" location (generally a data reg) is incorrect with respect to the program flow.

Here information copied in the ID stage at line 2 will be the previous value of $t1, as the new one will be copied at the end of WB stage of instruction 1 (and hence at the end of MEM stage of instr 2).

Forwarding means discarding the regular information and replacing it by the new (and correct value). It can be done

1/ as soon as the new value is available in the processor. Lets call t_a this time

2/ up to the last time that this information is required (because it will be transformed by the ALU, written to the mem, etc). Lets call t_u this instant

If t_a <= t_u, simple forwarding can be done. Otherwise one or more stalls are required.

Lets look at the code

1 addi $t1,$zero,0x30
2 lw $t2,0($t1)

Say Stage IF of instr 1 is t1, ID t2, etc

1 the new value of $t1 will be available at the end of stage WB (t5)

2 the value of $t1 is read at the start of ID stage (t3)

There is a data hazard.

When is the information associated with $t1 available ? After EX stage of 1. So t_a=t3

When is the last time that this information is required by instruction 2 ? Just before the adresse (0+$t1) is computed by the ALU. I.e. t_u=t4

There is no need of any stall. The value read in $t1 register is just discarded and replaced by the one in the ppline register.

Consider now instructions 2 and 3.

2 lw $t2,0($t1)  
3 sw $t2,0xff18($zero) 

There is a hasard as $t2 is written at the end of WB stage of inst 2 (t6) and read at the beginning of ID stage of inst 3 (t4).

When if the information associated with $t2 available in the processor. At the end of MEM of instr 2 it is written in some ppline reg of the proc (t5=t_a).

When is this information required ? Just before writing to the memory by inst 3. After it is too late. That is at the start of MEM stage of inst 3 t6=t_u.

Again a simple forward can solve the problem.

(note that if instr 3 had been sw $t5,0xff18($t2) the situation would have been different. $t2 would have been required for the address computation (start of EX stage of inst 3 at t5), that is before its production (end of MEM of instr 2 t5), and a stall would have been required over the forwarding.)

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  • $\begingroup$ Ok, so for lw instructions, the result is first available in the end of MEM stage because it returns a memory address, but for instructions such as add, sub etc has result first available in the end of EX stage, did I understand correct? $\endgroup$ – nihulus Jan 9 at 21:10
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    $\begingroup$ Before the MEM stage, data is in memory, not in processor. During the mem stage, it is copied from memory to the pipeline regs and is available for forwarding. For other instructions, it can be forwarded as soon as it is omputed (ie after the EX stage). $\endgroup$ – Alain Merigot Jan 9 at 22:16

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