I'm coming to you today because I have some trouble to understand how works D flip flop in depth. Two weeks ago we started at school learning sequential logic and so register and everything that come with. We saw how to build a D flip flop using RS Asynchronous flip flop like this one :
Then we made a synchronous version of this one using two AND logic gate (one per input) and a clock input. The D flip flop we made is only a RS Asynchronous using only one input linked to S, and the NOT linked to R. Just like this :
I was conviced that it's the good way. It works on falling edge so it's perfect for shift register. And then my teacher told me that we couldn't use any gate on clock (in my case I use a NOT gate). But he can't tell me clearly how to do a D flip flop working on rising or falling edge. Even if Logisim (the software I use to simulate circuits) there is a D flip flop where you can make it working on Rising, falling edge or even at high or low level. So my main question is : What is the good way to make a D flip flop working or RISING or FALLING edge if we can't use a single gate on clock ? And why can't we use gate on clock ?