# If a NAND gate is universal, why you don't have NAND OISCs

If a NAND gate can be used to construct all other of the basic logic gates, then I'm wondering why you don't/can't have a purely NAND-based One Instruction Set Computer (OISC). All the OISC single instructions are complicated like "addleq, add and branch if less than or equal to zero", but I don't see why you can't just have an OISC be "nand, perform nand operation". Wondering what I am missing.

• Without branching, the best you can do is a very long sequence of nand operations. Doesn't sound very general to me. – gnasher729 Mar 4 '19 at 0:46
• @gnasher729 most likely the following works: Define $ip := \texttt{Mem[}0\texttt{]}$ and transpile each addleq instruction using $\big[\texttt{Mem[}1\texttt{]},\dots,\texttt{Mem[}N\texttt{]}\big]$ as scratch space into a (very) long nand-sequence. $N$ depends on word size, but fix and therefore you can use the remaining memory for programming. – KVN Mar 4 '19 at 0:58
• (even if $N$ wasn't fix, you could use even/odd indexing or the like) – KVN Mar 4 '19 at 1:01
• Actually, not sure if this works since nand is not able to propagate bits, more trickery is needed (defining nand to work on $\texttt{Mem[}a\texttt{]}_i$ and $\texttt{Mem[}b\texttt{]}_{i+1}$ could work?). – KVN Mar 4 '19 at 1:08

So if every NAND gate in your "computer" has a address, and the list of instructions is of the form inputA,inputB you might have a start on a "computer" with one instruction that's a NAND. (I think you'll have to come up with a parallel semantics, no instruction pointer.)
• What prevents us to modify the instruction pointer in case it's stored at memory location $0$? – KVN Mar 4 '19 at 1:28
• Different (even more interesting, but more tricky to get right) idea: Initially $\texttt{Mem[}0\texttt{]}$ is non-zero, the program will loop indefinitely until said memory location is zero. Pretty sure this will work too. – KVN Mar 4 '19 at 1:31