# How do I get the NAND gate configuration for full adder from the logic table?

I'm self-studying, but I've gotten stuck already. If I'm given the logic table for a full-adder or any two-output table, how do I figure out the NAND-gate configuration, preferably methodically? Specifically, given the table:

x y z | 2^1 2^0
0 0 0 |  0   0
1 0 0 |  0   1
0 1 0 |  0   1
0 0 1 |  0   1
1 1 0 |  1   0
0 1 1 |  1   0
1 0 1 |  1   0
1 1 1 |  1   1


How do I find the following set-up:

So far, I've gotten:

x'yz+xy'z+xyz'+xyz=x(yz'+y'z)+xy

xy'z'+x'yz'+x'y'z+xyz=x'(yz'+y'z)+x(y'z'+yz)

I can see the first XOR gate between A and B in the diagram and I can see the yz'+y'z XOR gate, but I'm not sure how to proceed from there.