# How to understand the SR Latch

I can't wrap my head around how the SR Latch works. Seemingly, you plug an input line from R, and another from S, and you are supposed to get results in $Q$ and $Q'$.

However, both R and S require input from the other's output, and the other's output requires input from the other other's output. What comes first the chicken or the egg??

When you first plug this circuit in, how does it get started?

• which book you are reading ? The book by Morris Mano explains this better. I suggest you to have a look at it. – avi Mar 22 '13 at 5:02
• For the better understanding of SR Latch thoroughly and how it behaves for the different inputs like 00, 01, 10 and 11 check this video out. www.youtube.com/watch?v=VtVIDgilwlA‎ – user12771 Jan 12 '14 at 6:55
• Note this repost on Electrical Engineering which has also attracted (good) answers. – Raphael Jan 12 '14 at 13:33
• another way to visualize/understand this is as a feedback loop where prior states are forced to new states. in other words it works no matter what the prior feedback states are. this can be worked through on a case-by-case basis as in the answer. – vzn Jan 12 '14 at 18:25

## 1 Answer

A flip-flop is implemented as a bi-stable multivibrator; therefore, Q and Q' are guaranteed to be the inverse of each other except for when S=1, R=1, which is not allowed. The excitation table for the SR flip-flop is helpful in understanding what occurs when signals are applied to the inputs.

S R  Q(t) Q(t+1)
----------------
0 x   0     0
1 0   0     1
0 1   1     0
x 0   1     1


The outputs Q and Q' will rapidly change states and come to rest at a steady state after signals have been applied to S and R.

Example 1: Q(t) = 0, Q'(t) = 1, S = 0, R = 0.

State 1: Q(t+1 state 1)  = NOT(R OR Q'(t)) = NOT(0 OR 1) = 0
Q'(t+1 state 1) = NOT(S OR Q(t)) =  NOT(0 OR 0) = 1

State 2: Q(t+1 state 1)  = NOT(R OR Q'(t+1 state 1)) = NOT(0 OR 1) = 0
Q'(t+1 state 2) = NOT(S OR Q(t+1 state 1))  =  NOT(0 OR 0) = 1

Since the outputs did not change, we have reached a steady state; therefore, Q(t+1) = 0, Q'(t+1) = 1.

Example 2: Q(t) = 0, Q'(t) = 1, S = 0, R = 1

State 1: Q(t+1 state 1)  = NOT(R OR Q'(t)) = NOT(1 OR 1) = 0
Q'(t+1 state 1) = NOT(S OR Q(t))  = NOT(0 OR 0) = 1

State 2: Q(t+1 state 2)  = NOT(R OR Q'(t+1 state 1)) = NOT(1 OR 1) = 0
Q'(t+1 state 2) = NOT(S OR Q(t+1 state 1))  =  NOT(0 OR 0) = 1

We have reached a steady state; therefore, Q(t+1) = 0, Q'(t+1) = 1.

Example 3: Q(t) = 0, Q'(t) = 1, S = 1, R = 0

State 1: Q(t+1 state 1)  = NOT(R OR Q'(t)) = NOT(0 OR 1) = 0
Q'(t+1 state 1) = NOT(S OR Q(t)) =  NOT(1 OR 0) = 0

State 2: Q(t+1 state 2)  = NOT(R OR Q'(t+1 state 1)) = NOT(0 OR 0) = 1
Q'(t+1 state 2) = NOT(S OR Q(t+1 state 1))  = NOT(1 OR 0) = 0

State 3: Q(t+1 state 3)  = NOT(R OR Q'(t+1 state 2)) = NOT(0 OR 0) = 1
Q'(t+1 state 3) = NOT(S OR Q(t+1 state 2))  = NOT(1 OR 1) = 0

We have reached a steady state; therefore, Q(t+1) = 1, Q'(t+1) = 0.

Example 4: Q(t) = 1, Q'(t) = 0, S = 1, R = 0

State 1: Q(t+1 state 1)  = NOT(R OR Q'(t)) = NOT(0 OR 0) = 1
Q'(t+1 state 1) = NOT(S OR Q(t)) =  NOT(1 OR 1) = 0

State 2: Q(t+1 state 2)  = NOT(R OR Q'(t+1 state 1)) = NOT(0 OR 0) = 1
Q'(t+1 state 2) = NOT(S OR Q(t+1 state 1))  = NOT(1 OR 1) = 0

We have reached a steady state; therefore, Q(t+1) = 1, Q'(t+1) = 0.

Example 5: Q(t) = 1, Q'(t) = 0, S = 0, R = 0

State 1: Q(t+1 state 1)  = NOT(R OR Q'(t)) = NOT(0 OR 0) = 1
Q'(t+1 state 1) = NOT(S OR Q(t)) =  NOT(0 OR 1) = 0

State 2: Q(t+1 state 2)  = NOT(R OR Q'(t+1 state 1)) = NOT(0 OR 0) = 1
Q'(t+1 state 2) = NOT(S OR Q(t+1 state 1))  = NOT(0 OR 1) = 0

We have reached a steady; state therefore, Q(t+1) = 1, Q'(t+1) = 0.

With Q=0, Q'=0, S=0, and R=0, an SR flip-flop will oscillate until one of the inputs is set to 1.

Example 6: Q(t) = 0, Q'(t) = 0, S = 0, R = 0

State 1: Q(t+1 state 1)  = NOT(R OR Q'(t)) = NOT(0 OR 0) = 1
Q'(t+1 state 1) = NOT(S OR Q(t)) =  NOT(0 OR 0) = 1

State 2: Q(t+1 state 2)  = NOT(R OR Q'(t+1 state 1)) = NOT(0 OR 1) = 0
Q'(t+1 state 2) = NOT(S OR Q(t+1 state 1))  = NOT(0 OR 1) = 0

State 3: Q(t+1 state 3)  = NOT(R OR Q'(t+1 state 2)) = NOT(0 OR 0) = 1
Q'(t+1 state 3) = NOT(S OR Q(t+1 state 2)) =  NOT(0 OR 0) = 1

State 4: Q(t+1 state 4)  = NOT(R OR Q'(t+1 state 3)) = NOT(0 OR 1) = 0
Q'(t+1 state 4) = NOT(S OR Q(t+1 state 3))  = NOT(0 OR 1) = 0

As one can see, a steady state is not possible until one of the inputs is set to 1 (which is usually handled by power-on reset circuitry).