I'm taking a course in computer architecture in which the main reference is the Computer Organization and Design by Patterson and Hennessy. I came across an example which I couldn't grasp its answer:

Example: how many total bits are required for a direct-mapped cache with 16 KiB of data and 4-word blocks, assuming a 32-bit address?

In the answer it says "We know that 16 KiB is 4096 (2^12) words. With a block size of 4 words (2^2), there are 1024 (2^10) blocks".

But how do we know how many words would be 16 KiB?

And then it goes on and says the total bits are (number of blocks) * (data (32 * 4) + tag and validation bits). why don't we count index or offset bits in total bits?

And finally it says number of tag bits is (32 - 10 - 2 -2). we have 10 bits for the index part, 2 bits for offset, what's the second 2 bits we are subtracting from 32?

Honestly I think I have missed something when studying the textbook, or there are some assumptions I'm missing.

BTW the answer according to the textbook is 147 Kibibits (18.4 KiB).

  • $\begingroup$ It seems they imply 4-byte words, so 16 KiB is 4096 words and "second 2" probably is logb(4) $\endgroup$ – Bulat Apr 10 at 22:12
  • $\begingroup$ See cs.stackexchange.com/a/43876 $\endgroup$ – Ran G. Apr 20 at 15:37

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