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I had a question in my past System Architecture exam and I am not sure how to solve it.
Question was this:
Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 bits and a block in memory is 8 bytes sized. Find $t$, $r$ and $w$ (they are Tag, cache index, and block offset respectively.)
Can you show steps of solution of this and such questions? Should I divide cache size by 2 since it is 2 byte addressable? Thanks.
I think i found out the solution, may be helpful for others reading this.
The size of a block is 8 bytes. And the memory is adressed with 2 bytes. So each block contains 4 words (considering 1 adressible unit = 1 word).
4 = 2^2, Then $w$ = 2 bits
Since cache has a size of 64 bytes which is 2^6, than $r$ + $w$ must be 6.
$r$ + $w$ = 6, $w$ = 2 so $r$ = 6-2 = 4 bits
Lastly the MAR is 10 bits so the length of RA ($r$ + $w$ + $t$) must be 10.
$r$ + $w$ + $t$ = 10, $r$ + $w$ = 6, then $t$ = 10 - 6 = 4 bits .
So the RA distribution will be like:
+----------------------------------------+
| t = 4 | r = 4 | w = 2 |
+----------------------------------------+