# Finding $t$, $r$ and $w$ in Cache - Direct Mapping

I had a question in my past System Architecture exam and I am not sure how to solve it.

Consider a 16-bit addressable memory and a direct-mapped cache sized 64 bytes. MAR is 10 bits and a block in memory is 8 bytes sized. Find $$t$$, $$r$$ and $$w$$ (they are Tag, cache index, and block offset respectively.)

Can you show steps of solution of this and such questions? Should I divide cache size by 2 since it is 2 byte addressable? Thanks.

• We discourage "please check whether my answer is correct" questions, as only "yes/no" answers are possible, which won't help you or future visitors. See here and here. Can you edit your post to ask about a specific conceptual issue you're uncertain about? As a rule of thumb, a good conceptual question should be useful even to someone who isn't looking at the problem you happen to be working on. If you just need someone to check your work, you might seek out a friend, classmate, or teacher. – dkaeae Apr 12 '19 at 15:04
• @dkaeae edited thanks – Muhammed Gül Apr 12 '19 at 16:02
• What are $t$, $r$, and $w$? Tag, cache index, and block offset? Please define these variables. – ryan Apr 12 '19 at 20:55
• @ryan yes they are, edited. Thanks – Muhammed Gül Apr 12 '19 at 21:01

I think i found out the solution, may be helpful for others reading this.

The size of a block is 8 bytes. And the memory is adressed with 2 bytes. So each block contains 4 words (considering 1 adressible unit = 1 word).

4 = 2^2, Then $$w$$ = 2 bits

Since cache has a size of 64 bytes which is 2^6, than $$r$$ + $$w$$ must be 6.

$$r$$ + $$w$$ = 6, $$w$$ = 2 so $$r$$ = 6-2 = 4 bits

Lastly the MAR is 10 bits so the length of RA ($$r$$ + $$w$$ + $$t$$) must be 10.

$$r$$ + $$w$$ + $$t$$ = 10, $$r$$ + $$w$$ = 6, then $$t$$ = 10 - 6 = 4 bits .

So the RA distribution will be like:

+----------------------------------------+
| t = 4 |       r = 4      |    w = 2    |
+----------------------------------------+