# Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this:

Consider stage latencies:

IF      ID      EX      MEM      WB
250ps   350ps   150ps   300ps    200ps


Consider instructions %:

ALU     BEQ     LW      SW
45%     20%     20%     15%


What is utilization of memory?

The solution given was:

LW and SW stages of pipeline use memory. Thus, 20 + 15 = 35%

However, I was guessing shouldnt we also consider stage latencies? That is , shouldnt this be $$\frac{300}{250+350+150+300+200}\times \frac{35}{100}$$ ?