If I have an address bus of 64K, i.e. it can access 64*1024 or 65536 locations, should I also have a memory chip with 65536 locations in it? What I'm trying to ask is that do all the 65536 locations that the address bus can address have a corresponding memory location? Or can some address bus values go unused? (Like when I have 65536 address locations but my memory chip has only 32768 locations) Is such a combination acceptable?
What you are looking for is named "address decoding".
If a processor can address 64kB, its address bus is something like A[15:0]. If you use a 1kB memory chip, its addresses will be A[9:0].
There are several options :
- Either you don't connect the bits A[15:10] of the processor. The memory will be mirrored at several "places" in the CPU address map, in this example, the same memory cell is accesssed at address 0, 1024, 2048, 3072, ... etc.
- Or you use additional hardware to select the memory chip only when A[15:10]=00000, for example, to map the RAM only between 0 and 1023, allowing to connect other chips and map them elsewhere in the address map : ROM, IO ports...
If a memory location is not mapped, when an read access is attempted, it will generate random noise, some default value or repeat the last access. This was true on simple CPUs (for example the old 8bits CPUs)
In more advanced architectures (typically build with 16 or 32bits CPUs), accesses to non mapped memories generates an exception usually named "Bus Error".