The Von Neumann architecture was first created in the mid 40s for use in a computing system known as ENIAC for research into the feasibility of thermonuclear weapons.

To this day the Von Neumann architeture is still primary foundation in the majority of modern computers. I have listened to a few historians and scientists mention that there is likely more efficient architectures and that Von Neumann himself didn't believe in its universal capability(unfortunately cannot remember enough to find a link).

So why do we still use this architecture in the majority of modern computing?

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    $\begingroup$ I think this question could improve a lot if you were to provide a source for your claims. Perhaps google may help you out? $\endgroup$
    – olinarr
    Apr 20, 2019 at 19:07
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    $\begingroup$ Because the statement "there is likely more efficient architectures" is wrong in practice. Computer designers do optimize the architectures to the very very very last bit, and found no sufficient reason to depart from Von Neumann. $\endgroup$
    – user16034
    May 4, 2022 at 10:12

5 Answers 5


So why do we still use this architecture in the majority of modern computing?

The assumption itself, first clause: Modern Computer <= Von Neumann

Firstly, do note that the Von Neumann architecture is not used exclusively: almost any current "Von Neumann" machine except for very small microcontrollers (which are occasionally Harvard machines) features several important extensions to the original architecture, from DMA to MMUs.

Specialized coprocessors are very popular - most notably, GPUs.

Those work very well in conjunction to a Von Neumann machine.

The assumption itself, second clause: Von Neumann <= Modern Computers

The limitations of the Von Neumann architecture and the need for non-Von Neumann architectures for certain applications is well recognized in the scientific community, most importantly whenever "[general] artificial intelligence" of interest, see for example this very recent paper, which continues the line of work started by Carver Mead, who envisioned one of the most radical departures from "classical" architectures in 1989, in the form of analog, time-continuous, highly parallel "neuromorphic" chips.

Your premise is thus, in a way, flawed, unless it is implied that you're referring purely to industrial applications (read on for that part).

On the notion of efficiency

Note that Mead himself had envisioned his architecture as complementary to a traditional Von Neumann machine.


This brings us to another important point: you mention "more efficient architectures", but efficient for which sort of workload?

Sontag and Siegelmann have famously proved that a feed forward neural network is Turing-complete, as is, of course, the Von Neumann architecture, and if we accept Church's thesis (which has never been seriously challenged in quite a while) that this amounts to the ability to compute all computable functions, they're theoretically interchangeable and unsurpassed in their abilities.

However, leaving aside for a moment the issue of practicality, they are not as efficient for the same applications.

I'm guessing that a neuromorphic chip such as Carver Mead's would make for a terrible Excel machine.

So why mostly Von Neumann in industrial applications?

But yes: even if research has branched in other directions and has gotten to the status of prototypes and early industrial devices Von Neumann architectures are still the bread and butter of industrial applications (and a good foundation to extend with coprocessors and specialized optimizations).

It's safe to assume that the reason is practical:

  1. They're universal -- i.e. "good enough" in the broadest possible sense: they are Turing complete and sufficiently close to some theoretical models such as the TM itself or the URM; it is safe to assume that the ubiquity of the Von Neumann machine has influenced developement of theory as well.
  2. They're tolerably easy to reason about and very well understood by engineers and developers
  3. They work very well for existing industrial workloads that drive the demand for hardware R&D; there is 60 years' worth of algorithms and software for Von Neumann machines.

Von Neumann closed under copper cable?

Finally - and only partly tongue-in-cheek: do note that it is very easy to obtain a decidedly non-Von Neumann machine from off-the-shelf parts: just buy two laptops and connect them with an UTP cable and you have a very strange machine where you don't have uniform, synchronized access to a single mutable storage or a single clock.

  • $\begingroup$ Man, I'm very upset so low up-votes this answer has! $\endgroup$
    – tamerlaha
    Jan 24 at 5:00

A competing architecture needs to tick these boxes reasonably well:

Doing stuff we want

Nobody will use it unless nearly all features available in popular high-level languages are supported reasonably efficiently. You can check out this paper with a provocative title: The von Neumann Architecture Is Due for Retirement. It outlines a lot of the challenges in departing from an architecture with a linear addressed memory. In particular:

... dynamic data structures cannot be efficiently represented in the basic dataflow model, and neither can dynamic behaviour, such as function calls, function pointers, code-as-data, and pass-by-reference. Previous attempts to overcome these limitations typically involved assuming a shared global memory and either adding load and store instructions or introducing other primitives which took advantage of the global memory (such as I-structures)

Letting engineers get things done

The von Neumann architecture very easily (compared to other models) allows for:

  • single-stepping through code
  • profiling code
  • graceful exception handling
  • implementing compilers
  • limiting compute/memory resources (i.e. CPU time and memory usage)
  • intuitiveness for programmers (step-by-step is about as simple as it gets)

Another important feature is reasoning about execution time, however the von Neumann architecture doesn't make this so easy anymore. In the past it did, but now this is thwarted due to deeeep cache hierarchies, parallel processing, swap space, and various forms of optimisation. Nonetheless, sequential code and dead-simple calculation of memory usage still go a long way which is why we learn Big-O analysis.

The von Neumann model also makes it reasonably easy (in theory) for hardware designers to build CPUs, memories, and the links between them. (In practice, today the more powerful CPUs analyse sequential instructions to build a dependency graph, basically a dataflow graph, funnily enough.)

Chicken and Egg (aka Inertia problem)

Companies won't invest billions developing new hardware if users won't flock to it. And they won't flock to it if they can't use their existing software on it. (The only reason ARM is so common on mobile platforms is because people were quite happy to only use software that they hadn't used before.)

If you look at the Intel 64-bit instruction set, it is riddled with stuff from the 16- and 32-bit days. (In fact you can run practically any software from the DOS days on a modern processor.) It will not be so easy for a radically different hardware architecture to be backwards-compatible.

The only realistic way for a competing architecture to become mainstream is if it is really good in some niche (like say physics simulations) and as it gains traction more and more is spent on improving its performance and generality until it starts to move to a wider domain. In a sense this is exactly what happened with graphics cards, but they are still just a glorified multiprocessor von Neumann architecture.

  • $\begingroup$ Just saying: The ARM 64bit chip in your iPhone can't run 32 bit code anymore. $\endgroup$
    – gnasher729
    Nov 29, 2019 at 23:52

Hardware can be directly memory mapped as long as it obeys the logic voltage and current rules of the system and worked on live with an interpreted language such as FORTH. I have had new chips up and running in 15 minutes using a 68HC11 running FORTH and debug problems on wireless systems half a world away on the same system running the FORTH interpreter on the what remained in SRAM when a C program crashed.

Many if not most things in industry can be done using a network of simple computers that work in low latency real-time with Unix or Linux box all disk I/O, time synchronization, serving up any complex work that's needed, etc.


It's been a few years since this question, but even at the time that the question was written, we don't. As several commenters point out, the overwhelming majority of CPUs that you can buy today use a Harvard architecture, with separate instruction and data memory.

This is true from microcontrollers, which typically have read-only instruction memories implemented with flash, through to high-performance CPUs, which use a modified Harvard architecture implemented with split instruction and data caches. It is especially true of GPUs, coprocessors, and other asymmetric multiprocessors.

But general-purpose CPUs still try to maintain the illusion of a von Neumann architecture under some circumstances. Intel still has a requirement to support self-modifying code, which seems silly in the 21st century, until you realise that this is still occasionally used to support debuggers.


Just an example - Volta GPU has 5120 so-called cores. Most modern CPUs has an out-of-order execution. Any modern processor has a lot of built-in caches. Do you still consider that as von-Neumann architectures?

  • $\begingroup$ I would say it is still Von Neumann-like, isn't it? $\endgroup$
    – olinarr
    Apr 20, 2019 at 19:02
  • $\begingroup$ May be. So how you define von-Neumann? $\endgroup$
    – Bulat
    Apr 20, 2019 at 19:06
  • $\begingroup$ I am by no means an expert, but I would say that a von neumann like architecture would have a logic/arithmetical unit, a control unit, central memory and I/O. I would think that what you cited in your answers are just improvements of this abstract model. $\endgroup$
    – olinarr
    Apr 20, 2019 at 19:09
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    $\begingroup$ They have caches, multiple cores, out-of-order execution and each year become closer to execution flow machines and active memory. $\endgroup$
    – Bulat
    Apr 21, 2019 at 4:56

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