# What architectural features will allow this microprocessor to access a separate "I/O space"?

I'm studying for my final and don't understand this question. Here is the full question (from Stallings 8th edition):

Consider a hypothetical microprocessor generating a 16-bit address (e.g., assume the program counter and the address registers are 16 bits wide) and having a 16-bit data bus.

a. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”?

b. What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”?

c. What architectural features will allow this microprocessor to access a separate “I/O space”?

d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain.

If I'm following, the answer to "a" is the processor is generating 2^16 = 64 Kbytes and the bus is 16-bit so the answer it 64 Kbytes.

However, for "b", the answer is 64 Kbytes are being generated but since the bus is only 8-bit, it requires twice as many cycles.

For the answer to "c", I am clueless and I think that carries over into me being clueless on "d". :-\

• for part c I think the answer could be the use of an expansion bus
– Abu
Dec 7 '19 at 20:35
• An 8086 processor with 16 bit PC and address registers could access 2^20 + 2^16 bytes of memory. Dec 8 '19 at 13:18

The CPU uses the same address/data bus to access both the memory space and the I/O space. They are however distinguished by an extra signal that tells whether the address/data is in the memory space or the I/O space. For instance, in x86 this signal is called $$M/\overline{IO}$$ (pin 28).
• the notation $M/\overline{IO}$ means $=1$ for memory and $=0$ for IO. Apr 21 '19 at 14:05
(For a) & b), my take is $$2^{16}$$ of whatever are addressable units - the bus size not being an indication (see e.g. Intel 8086↔8088). It does not read 16 address lines/signals, nor does it mention address multiplexing.