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I have come across about RS Flip Flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the case unstable or the forbidden case S=1, R=1 in Flip flop. Can anyone tell me what exactly is that?

By the way I have used 2-INPUT NAND Gates to implement the flip Flop. What is the difference between the NAND Gate Flip Flop & NOR Gate Flip Flop, ?

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closed as too localized by frafl, Gilles Apr 7 '13 at 15:18

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    $\begingroup$ Hello and Welcome, your question fits better in Electrical Engineering please ask there, and you'll get better answers. Thanks! (MODS - flag to migrate?) $\endgroup$ – Ran G. Mar 27 '13 at 0:35
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    $\begingroup$ @RanG. Is this question really off-topic here? $\endgroup$ – Gilles Mar 27 '13 at 1:00
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    $\begingroup$ @Gilles, yes, I believe so.. We need to draw a line, and this, IMHO, is a clear hardware, EE, signal-level issue. Let's continue in meta. $\endgroup$ – Ran G. Mar 27 '13 at 1:37
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    $\begingroup$ Besides the question whether this is ontopic, the question can be improved in terms of clarity in presentation, both in terms of language and what the actual question is. $\endgroup$ – Raphael Mar 27 '13 at 12:01
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    $\begingroup$ This question has been cross-posted and answered on EE.SE: electronics.stackexchange.com/questions/62501/… and the first question Gilles mentioned is on CS.SE, too: cs.stackexchange.com/questions/10614/…. This makes this one here a duplicate. $\endgroup$ – frafl Apr 4 '13 at 19:38
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This question has an accepted answer on another site.

Digest: If you had both inputs set to $1$, both outputs would be $0$ but they are supposed to be complementary.

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