# Comparing between single-cycled and Pipelined Processor

In order to ensure my understanding on the concept of pipelining is correct, I did some calculation (see below). Pls share your feedback on my understanding.

For a single cycle instruction set, assuming 400 ns for each cycle, I found, CPI=1.

Now, say, these instructions are 4 staged, and can be put in a pipelined architecture. With this we can change the clock cycle time to 400 ns/4(stage) = 100 ns. Further, assuming we've four no-inter-dependent instructions to execute, we see that CPI = 7 cycles/4 instructions = 7/4 [First instruction takes 4 cycles and next 3 instructions add only 3 cycles totaling 7 cycles for 4 instructions to finish.]

Pls, let me know if this is a correct understanding.