Clarification on interplay between cache line size and read/write sizes

Question

Say that you have cache lines with the size of 64 bytes and a set-associative or directly mapped cache. Let's also say that the word size is 8 bytes.

According to my understanding, we use a number of the most significant bits of a memory address in order to determine where in the cache to place the data. Am I correct in believing that, if I want load data starting from, for example, address 30, then all data starting from address 0 to 63 will be loaded into a cache line? Or will all data from address 30 to 93 be loaded?

If the former is the case, I assume that, if an instruction to load 16 bytes from address, say, 60, then this forces us to load two 64 byte cache lines (one line 0-63 and another 64-127). Is that correct or have I misunderstood something? Also, is this something that often occurs or are there reasons for why that isn't the case?

Answer 1

Cache lines always start at a byte address that is a multiple of the cache size, like 0, 64, 128 etc. If you need 8 bytes starting at byte 30, then the cache line containing bytes 0 to 63 will be loaded.

If you need 8 bytes starting at byte 60, then you need bytes from two cache lines, so the cache line from byte 0 to 63 is loaded, then the line from byte 64 to 127. (Since this is more complicated, it very much depends on the CPU how long this will take, usually anything from "a little bit longer" to "a lot longer". Compilers will usually try to align data to minimise the cost of data straddling cache lines).

Sometimes the cache line size is bigger than the amount of bytes that can be read from RAM in one operation (say 64 byte vs 32 bytes). Some CPUs can then read the "right" 32 bytes first and deliver the data to the CPU, while the rest of the cache is being loaded. So if you want bytes 40..47 the CPU may be able to load bytes 32..63 first, then give the 8 bytes to the CPU while loading the second half.