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While studying instruction pipelining in MIPS processor, we make an assumption that registers read/write stages take only a half clock cycle, as this picture shows (half clock cycles are dotted in register operations):
So what is the purpose of this assumption? and why is the fourth instruction in this graph is considered a hazard if we actually wrote the value of $2 in the first half clock cycle and then read it in the latter one?
By using different phases of a clock cycle for register write and register read, the number of register file ports can be reduced. (This can reduce area and latency.) A two-read and one-write instruction would otherwise require three register file ports (or introduce a structural hazard); by using different phases of the cycle one port can be used for both read and write. This can also facilitate reading from the register file in the same cycle as the value is written, which reduces the number of results that must be managed through the forwarding network.
The fourth instruction (add $14, $2, $2) does not have a data hazard even without forwarding.
