This is an online question I am trying to solve.

You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, 1.5ns, 4ns, 3ns, and 0.5ns, what is the best speedup you can get compared to the original processor?

Approach I: In a pipelined architecture, in a steady state, the CPI tends to be 1 provided there is no fixed percent of NOPs. Thus Speed up = CPI_non_pipelined / CPI_pipelined = 1.4 /1 = 1.4

Approach II: For converting the execution into pipelined, we need to reduce the cycle to match up phase duration. Thus pipelined cycle should be max of {phase durations} = max of {1ns, 1.5ns, 4ns, 3ns, and 0.5ns} = 4ns. So speed up = cycle_duration_non_pipelined / cycle_duration_pipelined = 10/4 = 2.5

Wondering why is this difference! Any help will be much appreciated.


Approach I is calculating the cycles per instruction change independent of frequency increase (presumably the unpipelined design has some hazards that are not present in the pipelined design forcing the unpipelined design to use multiple cycles for some instructions).

Approach II is calculating the frequency increase (cycle time decrease) from pipelining (ignoring overheads).

The actual performance increase, assuming a miraculous reduction of cycles per instruction from 1.4 to 1 and such foolishly unbalanced pipeline stages (and no overheads), would be the product of these two factors.

If the cycle time of the unpipelined design equals the total processing time of an instruction for the pipelined design, one would expect the CPI to be the same under ideal circumstances (no pipeline hazards). Somehow in this example, the unpipelined design manages to take longer on average to process an instruction than the pipelined design, which indicates that it is merely accidental that the times are equal; the stages of the pipelined design do not correspond to portions of the cycle time of the unpipelined design.

Pipelining does not reduce the amount of work and if each pipeline stage corresponds to an equal duration of work in the unpipelined design (i.e., work is not done faster) then the CPI would be equal, which implies that the pipelined design is not fully pipelined.

(Another alternative is that two distinct ISAs are being compared such that the more pipeline-friendly ISA used by the pipelined design uses 1.4 times as many instructions to avoid instructions that would take longer than 10ns to fully process.)

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    $\begingroup$ The question appears to be poorly developed even assuming spherical cow approximations. $\endgroup$ – Paul A. Clayton Jun 25 '19 at 18:45

Some guesswork is needed here.

CPU 1 takes 1.4 cycles per instruction on average, which means 60% of instructions take 1 cycle, and 40% take 2 cycles (or there may be some instructions taking 3 cycles or more, but we ignore this at the moment).

If an instruction takes two 10 nanosecond cycles, then it cannot be performed in a pipeline taking a total of ten nanoseconds, so CPU 2 probably split the 2 cycle instructions into two, meaning that CPU 2 needs to execute 40% more instructions than CPU 1. That's quite predictably the same 40% that CPU 1 on top of each instruction. So the 40% more instructions make no difference.

What does make it difference is the 4 cycle pipeline speed, instead of 10 for COU 1. CPU 2 is 10/4 = 2.5 times faster.


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