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Is address translation for all operands in single instruction done only once and then are all operands fetched continuously?

For example, consider any dummy instruction INSTR with two operatnds OP1 and OP2:

INSTR OP1, OP2

How does an operating system map logical addresses of these operands to their physical addresses? Is this address translation done only once for each instruction and then are all operands stored in consecutive memory locations? Or is address translation done separately for each operand and hence page tables are referenced for each operand separately?

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Usually instructions are moved from RAM or from external memory to the processor’s instruction cache. Then the only address mapping is mapping a logical address to a cache line containing the instructions.

Most instructions are completely contained within one cache line, on processors with fixed instruction size each instruction is contained within one cache line. On processors with variable instruction length like intel processors the instruction decoder will read two cache lines if needed.

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  • $\begingroup$ Just to reconfirm, this implies that the address translation is done only once for the instruction which fetches opcode with all operands. No need to do explicit address translation for any operand. $\endgroup$ – anir Aug 7 at 15:45

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