I'm trying to read the book 'Digital Design Computer Architecture'.
In the part of Performance Analysis(7.3.4 in the book), Author refers to clock cycle for MIPS single cycle processor. But I think there's something wrong with author's evaluating clock cycle.
T(Clock cycle) = T(pcq_pc) + T(mem) + Max[tRfread, t(sext)] + t(Mux) + T(ALU) + T(mem) + t(mux) + T(RFsetup)
But I think clock cycle 'T' would be ( if T(RFread) > T(mux) + T(sext) )
T(Clock cycle) = T(pcq_pc) + T(mem) + T(RFread) + T(ALU) + T(mem) + T(mux) + T(Rfsetup)
Since I think the MUX followed by ALU already selects known sign-extend immediate before register value(the pin
RD1 in below diagram) is known.
and if T(RFread) is less than T(mux) plus T(sext).
T(Clock cycle) = T(pcq_pc) + T(mem) + T(sext) + T(Mux) + T(ALU) + T(mem) + T(mux) + T(RFsetup)
Some referenced information by the book.
- T(pcq_pc) is propagation delay for PC.
- T(mem) is read-propagation delay for instruction memory and data memory.
- T(sext) is propagation delay for Sign Extend logic.
- T(RFread) is read-progagation delay for register file.
- T(mux) is propagation delay for MUX.
- T(ALU) is propagation delay for ALU.
- T(RFsetup) is setup time for Register file.(Register value is written on positive clock edge)
Here is Diagram for MIPS single cycle CPU.
Is my thought correct? If you think author is right, Could you tell my why?
Any help would be awesome!