# Finding Cache Miss Penalty in Memoery with Banks

Following the same argument we compute the miss rate as 1/2Consider a memory system with 4 Gbyte of main memory, and a 256 Kbyte direct mapped cache with 128 byte lines. The main memory system is organized as 4 interleaved memory banks with a 50 cycle access time, where each bank can concurrently deliver one word. The instruction miss rate is 3% and the data miss rate is 4%. We find that 40% of all instructions generate a data memory reference. a. What is the miss penalty in cycles?

Taken from here

I could not figure out how a miss penalty of 440 cycles is calculated here. The solution given just says

Address cycles + access cycles + transfer time 8 + 8 x 50 + 32 = 440 cycles

My understanding is Miss Penalty (MP) = time for successful access at next level + (MR_next_level x MP_next_level)

Since, here next level is RAM itself, if we assume 100 HR (hit rate) then MR_next_level=0. So, MP(cache)=Access time RAM = 50 cycles. Further, about the 4 banks, if they would have not been there, then I presume the access timing would have been ~50x4 cycles.

Pls help me understand, what I'm missing.