I am reading about a counter implementation in RISC Architecture. The specification reads,

Sticky overflow bit is set when the counter wraps through zero.

I can infer that the overflow bit is set when the counter reaches maximum value(all 1's) and another increment makes it 0(all 0's). What is the meaning of the sticky overflow bit?


A sticky overflow bit means that the next operation that does not overflow (but would set the bit if it did) will not clear the bit. The value is sticky/persistent and must be cleared to detect newer overflows.

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  • $\begingroup$ Thank you very much for your answer $\endgroup$ – Anurag A S Oct 4 '19 at 1:56
  • $\begingroup$ Seems like an odd piece of design - does this mean the overflow bit has to be explicitly cleared before each and every arithmetic operation, to avoid false positives ? $\endgroup$ – gandalf61 Oct 4 '19 at 15:16

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