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I'm new to Computer Organization and even to this community. I didn't find anything which was simple, clear and up to the point. Any examples supporting the discussion is appreciated. I'm not looking for some text book answer.

Here's an example of my view to question: What is a Programmer's Model ? Programmer's model shows what the CPU has available to a programmer for the execution of computer programs. It covers the CPU resources for execution of the CPU's instruction set. (resources like state variables, AKA registers that can affect — or be affected by — the execution of instructions)

This programmer's model would NOT detail hardware, such as how the CPU's electronic circuitry works, how buses transport data or the I/O peripherals available. i.e. The underlying details of how all of that is actually accomplished are hidden from the programmer.

In other words, the programmer's model would NOT cover functions that cannot be observed by CPU instructions. [EXCEPTION: those instructions trying to detect hardware operations, such as cache behavior, read/write variances because of varying bus delays etc are excluded]

So, similarly I wish to know what is a Memory Model ?

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  • $\begingroup$ Welcome to CS@SE. Some questions answered here: memory model. Can you elaborate how a helpful answer differs from a textbook one? $\endgroup$
    – greybeard
    Nov 22 '19 at 9:04
  • $\begingroup$ @greybeard I've already searched for memory model on CS@SE. The line: I'm not looking for some text book answer, only meant to say that I'm expecting for an answer which can be easily understand without any jargon. Apologies, if I have hurt anyone. $\endgroup$ Nov 22 '19 at 9:49
  • $\begingroup$ Offence neither taken nor intended. I find it more difficult to reach useful assumptions about what a new contributor is not explicit about. From How do I ask a good question?: Sharing your research helps everyone. Tell us what you found and why it didn’t meet your needs. $\endgroup$
    – greybeard
    Nov 22 '19 at 10:05
  • $\begingroup$ I have added more details to express my question. Please tell me if I'm still not clear . And thank you for your effort @greybeard. I really appreciate the time and effort which is involved. $\endgroup$ Nov 22 '19 at 10:30
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    $\begingroup$ There's bound to be more than a handful of interpretations of memory model, with what I'd call the CS one featured in Doralisa's answer. Another one assumed in resource usage analysis in the definitions of the abstract machines, notably RAM. $\endgroup$
    – greybeard
    Nov 22 '19 at 19:20
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um I'm not sure if it is what you are looking for or not. I assume by memory model you mean the part in which we place input and do some calculation (like paper which we write something to remember and calculate).

The memory model depends on the definition of the model itself. In CS we have different kinds of computing model with different power. One of the simplest one is Deterministic Finite Automata and informally its memory just contains an input string and nothing more. One of the most powerful one is Turing machine that its memory is a infinite tape. There are other models between these two such as PushDown Automata and Linear Bounded Automata where loosely speaking their memories contains stack of symbols and finite tape.

Also there are other models with same power as Turing machine, like two stack PDA, cellular automata and etc.

So by how to define your computing model and program, your memory model details will be different.

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  • $\begingroup$ I came across the term "memory model" when I was reading the following book (mentioned in link below) on page 5 of the book (which is page 32 of pdf file) and 2nd paragraph the line says as follows: The ARMv7-M architecture contains the following key areas: • Programmer’s model • Instruction set • Memory model • Debug architecture $\endgroup$ Nov 23 '19 at 4:49
  • $\begingroup$ reference to the link mentioned above: eecs.umich.edu/courses/eecs373/labs/refs/M3%20Guide.pdf $\endgroup$ Nov 23 '19 at 4:51
  • $\begingroup$ @PrajwalShetye Unfortunately I'm I don't know about structure of chips hardware. It seems that page 10 of the book says you can find more about the details of memory model in another book. I just can guess that memory model in this context is kind of structure in which helps not only store data but also hasten computing. $\endgroup$
    – Doralisa
    Nov 23 '19 at 19:21
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If you have a single thread program, with no memory shared with any other threads, then you essentially have a a single-CPU machine. There is only one opinion on the contents of memory, and that is yours.

When you have multiple CPUs, you have the issue that different CPUs can try to modify the same memory at the same time. If those CPUs have caches, it's possible that the caches will flushed in a different order than the original writes occurred.

This means that, if you're not careful, the contents of "memory" could look different to different CPUs. Moreover, different CPUs might see the same memory operations happen in a different order.

To see why this is important, consider what happens when you acquire or release a lock.

We will assume that acquiring a lock is just a write to memory (a spinlock really is just that). Then it's important that any memory operations which are protected by the lock happen after the acquisition occurs. Similarly, any writes to memory need to happen before the lock is released.

You can think of a memory model as a set of restrictions on how much a CPU (and a compiler, for that matter) can reorder memory operations. The way that this is usually presented is mathematically, as a set of "happens-before" relations. Memory operations protected by a lock must "happen before" the lock is released.

Apart from giving guarantees that certain things will happen before certain other things, programmers can control this by using special operations such as memory barriers. So, for example, there will typically be a memory barrier right before the store operation that releases a spinlock.

Even in CPUs with very strict memory models, you sometimes need consider the language's memory model to get multiprocessor algorithms working correctly. Many compilers have a way for you to write an "optimisation barrier", which prevents the compiler from reordering code across the barrier.

As an example, there's a good introduction to Java's memory model.

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  • $\begingroup$ If I/O devices can access memory, then even a uniprocessor can have more than one view of memory. Non-cache-coherent I/O (where it is software's responsibility to either use non-cacheable memory or explicitly ensure write to memory before access by an I/O device) complicates the model. Hardware guarantees about aliases is also involved. There can also be different behavior for non-temporal stores. $\endgroup$ Jan 11 at 20:35
  • $\begingroup$ That's true. Memory-mapped IO requires non-cached access. I'm not a hardware designer, but I believe that DMA isn't as much of a problem, because coherence between the DMA controller and CPU caches can be handled using the normal cache coherency mechanism. $\endgroup$
    – Pseudonym
    Jan 11 at 23:33

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