1
$\begingroup$

Suppose that we have 5 different instruction categories (1 OP, 2 OP, 0 OP, branch, and sub-routine instructions), how does a CPU manage to know which category is which whenever it reads an instruction from IR register using the least number of bits for each category? For instance, PDP-11 uses 4 bits (15 → 9) for two-operand instructions and 10 bits (15 → 8) for one-operand ones to denote the opcode of a particular instruction, how does it identify in the first place whether it's a two-operand or a one-operand instruction so that it would read the first 4 or 10 bits accordingly?

$\endgroup$
1
$\begingroup$

Normally the opcode encoding is designed to make it easy to tell. The details of exactly how that works will depend on the particular architecture. For instance, in your example, the first 4 bits might be enough to determine which category the instruction is in. This decoding is performed by the instruction decoder.

As Ran G. explains,

usually, either all instructions have the same length -- and then different OPCODEs signify different operations, or the instructions have variable length, and then there is some sort of prefix-coding that allows the CPU to determine which instruction it is (and what it length is) by its prefix.

$\endgroup$
  • 2
    $\begingroup$ Just to add that usually, either all instructions have the same length -- and then different OPCODEs signify different operations, or the instructions have variable length, and then there is some sort of prefix-coding that allows the CPU to determine which instruction it is (and what it length is) by its prefix. $\endgroup$ – Ran G. Nov 30 '19 at 13:01
0
$\begingroup$

In theory, the opcode is held in the instruction register (IR) until the instruction is complete. There is a cycle counter that is re-initialised each time a new instruction is started.

The IR controls what happens at each cycle. For example, with a 0-operand instruction, the program counter is not incremented until the end of the instruction. With a 2-operand instruction:

  • cycle 0: a fetch is done on the PC into IR
  • cycle 1: the program counter is incremented
  • cycle 2: a fetch is done on the PC into some internal register
  • cycle 3: the program counter is incremented again
  • cycle 4: another fetch is done on the PC into some internal register
  • cycle 5 onwards: the "work" of the instruction is performed
  • last cycle: the program counter is incremented so the next instruction is ready to go

The instruction decoder figures this out (whether or not it's easily represented within the bits of the opcode) and switches on the right circuits during the right cycle.

Of course this is just an example. Incrementing the program counter can easily be done at the same time as a fetch. Various 8-bit CPUs worked like this, but modern CPUs do crazy shenanigans so this probably doesn't apply to them except conceptually.

$\endgroup$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.