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I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design.

I suppose, that I should answer that what should be changed on architecture level.

I am familiar with the meaning of pipelining.

I came up with the following basic idea: registers should be added to hold the intermediate values between pipelining input and output, which should be controlled by a common clock (including i/o).

Is my idea a plausible answer to the question?

At my level, I do not think that I am supposed to give a working example for it, but I am happy so any.

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Pipline Example

This is an example of a pipelined architecture. You mainly put register files (which introduce some delays) to save data from one stage to another. Think of it like assembling a car, the chasis is done in one stage then it waits (in our case storage is the Register File (RF) then it goes for the other stage...
To implement pipelining properly, you need to equally divide the stages of the pipeline so that you can minimize clock cycle. The clock cycle will be the inverse of the time of the longest stage of the pipeline (longest delay between two RFs) which is usually (in realistic cases) determined by memory accesses stage of the pipeline.
Also note that you always need to save all signals (control and data) between one stage and another.
So all in all different instructions will be using different parts of the pipeline.

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If every complete operation takes one cycle, then pipelining using the same cycle time won't give you any advantage whatsoever.

What you would do is to split up each operation in various parts. First you make the cycle say four times shorter, so now each operation executes in four cycles. Then you split each operation into say five parts, and you have a first stage doing the first part and moving the results to the second stage, then a second stage doing the second part and moving it to the third stage, and so on. It will take all in all a little bit longer because you need the time to move data from one stage to the next.

And now you have five different stages, you can start pipelining. The first stage does the first part and moves the result to the second stage in the first cycle, and in the second cycle it starts work on the first part of the next instruction and so on.

You win because now the cycle time is four times shorter, so you can do up to four times more operations per second, working on up to five instructions at the same time.

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