I was asked that how can one make a single cycle processor pipelined on a CS course without any specifications regarding the design.
I suppose, that I should answer that what should be changed on architecture level.
I am familiar with the meaning of pipelining.
I came up with the following basic idea: registers should be added to hold the intermediate values between pipelining input and output, which should be controlled by a common clock (including i/o).
Is my idea a plausible answer to the question?
At my level, I do not think that I am supposed to give a working example for it, but I am happy so any.