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Pre-information:

I'm sure someone has asked something along these lines, but no matter how I word it, I can't seem to find a definitive answer

Question:

Does RAM get some kind of indication as to how much data the CPU requires or is there a set amount of data and if the CPU needs more, it needs to call again (and what is that set amount of data).

During a cache miss, the CPU will require at least a single cache line (32, 64 or 128 bytes). Does the CPU need to query RAM multiple times to get a single cache line (assuming the set amount is 8 bytes) or does the RAM return more data per call or does RAM have some way of being notified as to how much data is required?

I'm aware the CPU is most likely going to call more than just a single cache line to avoid the lengthy request from RAM if more data is needed in future from the same block of memory.

Extra Points:

If you do know and have more information, the following extras would also interest me:

  • If this is different depending on CPU make (generational differences can also be interesting but if you do add information about that, please skip similar generations)
  • If this is different depending on RAM type
  • How the CPU can request a different sized cache line or block size (only applies if RAM returns a fixed size that's the size of a block or cache line)
  • Any other useful relevant information or resources for further reading

Potential answer:

I seem to have found a clue to the answer when looking at the transfer rate of RAM, specifically where it indicates how to calculate the transfer rate from the specifications and from "DDR SDRAM prefetch architecture" which indicates how many 64 bit "blocks" can be requested per call to RAM (e.g. 8 for DDR3 and DDR4, 4 for DDR2 and 2 for DDR1)

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In most modern hardware, main memory is more like a peripheral.

What I'm going to describe in what follows is Intel-esque PC-ish hardware, but it's very similar on other systems.

During initial booting, when the power is first applied, the CPU only has cache, firmware, and some memory-mapped I/O. One of the first jobs is to initialise an external piece of hardware traditionally known as the "memory controller" or "memory controller hub" (in PC hardware it's part of the northbridge), which communicates directly with RAM modules.

I say "RAM modules", because they are really like peripherals, as I said. The hardware asks the module how much memory is present, and also negotiate the details of the protocol they will use to transfer data to and from main memory.

Like other modern peripherals, modern RAM modules can burst reads and writes, that is, they can read and write a larger "block" of memory using one transfer operation. So even if the "last" level of cache operates with the same cache line size as lower-level caches, it can transfer larger blocks of data to and from RAM than that.

This is a useful optimisation when performing operations like linear scans through a block of memory. Some combination of the CPU and cache controllers can detect this, and use that information to issue a prefetch from RAM.

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  • $\begingroup$ Thanks, so just to make sure I understand correctly, RAM will be notified of the size of chunks that should be returned per single operation (such as 32 / 64 bytes for a cacheline as required by the CPU) and then the CPU's memory controller can send a single request for data which will return the consecutive data of the desired size initially agreed upon? Also, if you could help clarify the difference between your and @gnasher729's answer as they seem to be similar but with a slight conflict / variation (I would upvote, but my reputation is too low) $\endgroup$
    – Dan
    Mar 5, 2020 at 13:15
  • $\begingroup$ My answer is about systems that you plug RAM modules (e.g. DDR SDRAM) into. It doesn't cover devices with fixed RAM (which gnasher729's more or less describes), and neither answer covers NUMA architectures. The thing about RAM modules such as DDR is that they are smart devices. The memory controller tells the module "I want to read this much data from this address". The amount of data is variable; it could be any multiple of the module's data bus width. $\endgroup$
    – Pseudonym ♦
    Mar 6, 2020 at 5:00
  • $\begingroup$ So the amount can change dynamically depending on the CPU's desired amount of data at the moment of the call to RAM or is this only configurable on initialisation? $\endgroup$
    – Dan
    Mar 6, 2020 at 7:57
  • $\begingroup$ It depends on what the hardware is capable of. But if it helps, DMA transfers are usually much larger than a cache line in size. $\endgroup$
    – Pseudonym ♦
    Mar 7, 2020 at 1:41
  • $\begingroup$ Now that I'm more aware of the subject, I can appreciate the prefetch for the upcoming DDR5 being (at least leaked) to be 16n as opposed to DDR4 and DDR3 both being 8n and simply benefiting from a doubling of clock speed instead of prefetch size (16n being the ability to get up to 16 word sized chunks per call). DMA is more about transferring between RAM and a slower device and is usually done in blocks (memory devices being 4KiB currently), that much I know, but I was more interested in the lower level calls since DMA does the transfer over multiple calls. $\endgroup$
    – Dan
    Mar 9, 2020 at 9:21
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RAM just gets requests for data to move to/from the CPU (really the MMU). Data is moved in units of cache lines.

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Currently, cache sizes are usually so big that more than one transfer from RAM to cache is needed to completely load a cache line. But reading from RAM takes time for the RAM to receive the address of the data to be read, and then time for the actual transfer, and asking RAM to perform say four transfers in a row is much faster than accessing four random memory locations.

Some processors have a feature that allows them to tell RAM in which order to transfer different parts of a cache line. Say there are four transfers needed to fill a cache line, then you would like to load the quarter cache line first that is actually needed (and then fill the rest).

It would be possible to only partially fill a cache line (and proceed filling a different cache line instead of completely filling the first one).

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  • $\begingroup$ Thanks, I'm assuming you're referring to a 32 byte cacheline and 8 byte constant data size returned from RAM per call? Also, there seems to be a slight conflict between your and @Pseudonym's answers, could you help in clarifying on this difference? $\endgroup$
    – Dan
    Mar 5, 2020 at 13:19

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