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A program, when run on a processor with unified cache (Data and Instructions in same cache) results in 0.05 cache misses per instruction. Also 25% of overall instructions of the program are load/store type. For this case there will be __cache misses per memory access.

a)0.0417 b)0.0400 c)0.0385 d)0.0370 e)None

My approach:

Assume 100 instructions.

->For 100 instructions there will be 5 cache misses.

->For 100 instructions there will be 100 Instruction memory access and since 25% of instructions are load/store type there will be 25 data memory access.

->For each cache miss there is an extra memory access from the main memory => 5 extra accesses

->Hence Total number of Memory access = 100+25+5 = 130

->Cache misses per memory access = 5/130 = 0.0385

But the correct answer provided is option (b)0.0400

However if I don't consider the extra memory access for each cache miss then: Total memory accesses = 125

Hence cache misses per mem access = 5/125 = 0.0400, which is the answer given.

I don't know if I'm wrong to assume that there is an extra memory access at time of cache miss as it has to access both the main memory and the cache during this scenario. Can someone please clarify?

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